Practical files.
Ready for your next review.

Inside this file

• System requirements and assumptions
• Exact MPN, package and grade register
• Evidence / decision log
• Procurement handoff

Complete Markdown text. Open and edit it with a text editor.

# FPGA selection brief
FPGA.io / KB Group Co.,LTD · Version 1.0 · 2026-09-29

An editable planning worksheet. This is not a validated circuit, a vendor specification or replacement approval.

## 1. Define the job
- Project / revision:
- Function to implement:
- Input format, channel count and sample rate:
- Output format and throughput:
- Maximum acceptable latency (include units):
- Environment and required operating life:
- Prototype / production quantity and required date:

## 2. Separate requirements from assumptions
| Requirement | Minimum / maximum | Unit | Source or measurement | Open question |
|---|---|---|---|---|
| I/O by bank and voltage | | | | |
| Local memory capacity and port width | | | | |
| DSP operations and precision | | | | |
| Serial channel count / data rate / protocol | | | | |
| Processing or real-time control | | | | |
| Package and board constraints | | | | |

## 3. Record each exact ordering code
| Manufacturer | Full MPN | Package | Speed / temperature grade | Official document + revision |
|---|---|---|---|---|
| | | | | |

Do not compare another package's I/O or transceiver figures with this code. Logic cells, LUTs, logic elements and DSP blocks are architecture-specific; use target synthesis and implementation reports for a fit decision.

## 4. Evidence and decision log
| Check | Evidence | Result / unresolved issue | Owner |
|---|---|---|---|
| Device and package exist in manufacturer ordering information | | | |
| Resources map to the actual design | | | |
| Bank standards and dedicated pins fit | | | |
| Timing and power were evaluated for the implementation | | | |
| Tool release and license support are confirmed | | | |
| Lifecycle, stock, price and lead time are checked for quantity | | | |
| Pinout / PCB changes for an alternative are identified | | | |

## 5. Procurement handoff
- Requested full MPN and permitted alternatives (if any):
- Quantity, delivery country and target date:
- Traceability / inspection requirements:
- Who may approve a substitute:
- Chip-only or combined PCB/PCBA scope:

Use https://fpga.io/catalogue/ for source-linked device records and https://fpga.io/compare/ for an initial comparison. Supplier figures must be checked for the same quantity, currency and packing.

Permission: copy and adapt this FPGA.io worksheet for internal or commercial engineering work; retain this attribution in redistributed copies. No third-party manufacturer documents are included. No warranty of fitness or design approval is provided.

Inside this file

• Template: blank input cells and calculation formulas
• Example: 32 + 2 × 16 + 2 + 16 = 82 signal pins
• Dedicated power, ground and configuration pins are outside the count

Template + Example sheets. Open in an Excel-compatible spreadsheet application. These XLSX files contain no macros.

82 pins establishes demand, not proof that a specific package fits.

Inside this file

• Device and document identity
• I/O bank allocation table
• Power rail assumptions and sequence
• Bring-up observations and review outcome

Complete Markdown text. Open and edit it with a text editor.

# FPGA I/O and power review worksheet
FPGA.io / KB Group Co.,LTD · Version 1.0 · 2026-09-29

Complete this worksheet from the exact device/package pinout and the implemented design. Blank cells are unresolved checks, not zero requirements.

## Identity
- Full MPN / package / grade:
- Schematic revision and date:
- Pinout document and revision:
- Electrical data sheet and revision:
- Tool release / device support:

## I/O bank allocation
| Signal group | Count | Direction | I/O standard | Bank supply | Clock / special pins | Pinout evidence |
|---|---|---|---|---|---|---|
| | | | | | | |

Check dedicated configuration pins, clock-capable pins, differential pairs, bank restrictions and reserved signals before counting spare pins. A package I/O total alone is not a valid bank allocation.

## Power rails
| Rail | Required voltage / tolerance | Estimated current | Estimation method / assumptions | Sequence | Regulator / distribution notes |
|---|---|---|---|---|---|
| | | | | | |

Use vendor power tools with actual activity, clocking, resources and temperature assumptions. A generic resource count cannot establish board current or thermal performance. Keep regulator input range, startup, decoupling and distribution analysis as separate checks.

## Bring-up observations to plan
| Observation | Measurement point | Instrument / setup | Acceptance criterion + source | Result |
|---|---|---|---|---|
| Rail ramp and sequence | | | | |
| Reset / configuration status | | | | |
| Reference clocks | | | | |
| Programming access | | | | |
| Interface activity | | | | |
| Temperature under defined workload | | | | |

Record instrumentation bandwidth and probe loading where relevant. Do not infer timing closure or signal integrity from an LED or successful programming alone.

## Review outcome
- Open issues and responsible person:
- Required schematic / constraints / layout changes:
- Conditions for moving to assembly:

Related planning tools: https://fpga.io/design-tools/io-budget/ and https://fpga.io/design-tools/power-rails/ . These organize inputs; the manufacturer's constraints remain authoritative.

Permission: copy and adapt this FPGA.io worksheet for internal or commercial engineering work; retain this attribution in redistributed copies. No third-party manufacturer documents are included. This planning aid does not approve a circuit or establish compliance.

Inside this file

• Template: two rail inputs and margin
• Example: 3.80 W load, 4.50 W input and 5.40 W with 20% margin
• An unused row needs explicit valid inputs; blank means unresolved

Template + Example sheets. Open in an Excel-compatible spreadsheet application. These XLSX files contain no macros.

These are fictional assumed currents, not specifications or a vendor power estimate for an FPGA.

Inside this file

• Project scope and file register
• Component / BGA review
• Inspection, programming and functional-test boundaries
• Release gate and approval references

Complete Markdown text. Open and edit it with a text editor.

# FPGA board manufacturing handoff
FPGA.io / KB Group Co.,LTD · Version 1.0 · 2026-09-29

Use one revision-controlled package for quotation and engineering review. This checklist does not state that a manufacturing capability or test service has been accepted.

## Project scope
- Project / PCB revision / assembly revision:
- Quantity and delivery schedule:
- PCB only / assembly only / sourcing plus assembly:
- Technical and purchasing contacts:
- Required inspection and documentation:

## File register
| Deliverable | Filename / revision | Included? | Owner | Open issue |
|---|---|---|---|---|
| Fabrication data and board outline | | | | |
| Stack-up and material requirements | | | | |
| Impedance requirements and applicable nets | | | | |
| Drill / via specification | | | | |
| BOM with exact manufacturer ordering codes | | | | |
| Centroid / placement data and coordinate convention | | | | |
| Assembly drawings and polarity markings | | | | |
| Programming files and release identification | | | | |
| Test procedure / fixture / acceptance criteria | | | | |

## Component and BGA review
- Approved alternates and named approval authority:
- Customer-supplied material, quantity and packing:
- Package drawings, land patterns and pin/ball maps:
- Moisture sensitivity / storage / handling requirements from supplier documentation:
- Assembly constraints and rework expectations:
- Traceability and inspection records requested:

## Test boundaries
| Requested check | Equipment / fixture responsibility | Acceptance criterion | Quoted / pending confirmation |
|---|---|---|---|
| Electrical / continuity | | | |
| Assembly inspection | | | |
| Programming | | | |
| Functional test | | | |

Distinguish inspection, programming and functional testing. An assembly quote does not automatically include a fixture, application firmware, environmental qualification or full functional coverage.

## Release gate
- All files refer to the same approved revision:
- Open engineering questions resolved by:
- Written sourcing / fabrication / assembly / test scope agreed:
- Approval reference and date:

Project preparation: https://fpga.io/engineering/
Manufacturing scope: https://fpga.io/pcba-bga-assembly/
Quotation: https://fpga.io/rfq/
Do not put confidential Gerber/BOM files or credentials into public forum questions.

Permission: copy and adapt this FPGA.io worksheet for internal or commercial engineering work; retain this attribution in redistributed copies. No third-party manufacturer documents are included. This checklist does not replace engineering release or a project-specific manufacturing agreement.

Inside this file

• Template: five deliverables with editable revision, owner and state
• Example: PCB/BOM Rev B versus placement Rev A
• State choices: Open, Ready, Mismatch, Not applicable

Template + Example sheets. Open in an Excel-compatible spreadsheet application. These XLSX files contain no macros.

The example deliberately contains a revision mismatch. “Ready” is a checklist state, not supplier acceptance.