Editable resources for device selection, I/O and power planning, and manufacturing handoff. See what is inside, choose the right format and keep a working copy.
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# FPGA selection brief
FPGA.io / KB Group Co.,LTD · Version 1.0 · 2026-09-29
An editable planning worksheet. This is not a validated circuit, a vendor specification or replacement approval.
## 1. Define the job
- Project / revision:
- Function to implement:
- Input format, channel count and sample rate:
- Output format and throughput:
- Maximum acceptable latency (include units):
- Environment and required operating life:
- Prototype / production quantity and required date:
## 2. Separate requirements from assumptions
| Requirement | Minimum / maximum | Unit | Source or measurement | Open question |
|---|---|---|---|---|
| I/O by bank and voltage | | | | |
| Local memory capacity and port width | | | | |
| DSP operations and precision | | | | |
| Serial channel count / data rate / protocol | | | | |
| Processing or real-time control | | | | |
| Package and board constraints | | | | |
## 3. Record each exact ordering code
| Manufacturer | Full MPN | Package | Speed / temperature grade | Official document + revision |
|---|---|---|---|---|
| | | | | |
Do not compare another package's I/O or transceiver figures with this code. Logic cells, LUTs, logic elements and DSP blocks are architecture-specific; use target synthesis and implementation reports for a fit decision.
## 4. Evidence and decision log
| Check | Evidence | Result / unresolved issue | Owner |
|---|---|---|---|
| Device and package exist in manufacturer ordering information | | | |
| Resources map to the actual design | | | |
| Bank standards and dedicated pins fit | | | |
| Timing and power were evaluated for the implementation | | | |
| Tool release and license support are confirmed | | | |
| Lifecycle, stock, price and lead time are checked for quantity | | | |
| Pinout / PCB changes for an alternative are identified | | | |
## 5. Procurement handoff
- Requested full MPN and permitted alternatives (if any):
- Quantity, delivery country and target date:
- Traceability / inspection requirements:
- Who may approve a substitute:
- Chip-only or combined PCB/PCBA scope:
Use https://fpga.io/catalogue/ for source-linked device records and https://fpga.io/compare/ for an initial comparison. Supplier figures must be checked for the same quantity, currency and packing.
Permission: copy and adapt this FPGA.io worksheet for internal or commercial engineering work; retain this attribution in redistributed copies. No third-party manufacturer documents are included. No warranty of fitness or design approval is provided.
Copy and adapt for internal or commercial engineering work. Retain FPGA.io attribution in redistributed copies. The checksum identifies this file version; it does not approve a design.
Copy and adapt for internal or commercial engineering work. Retain FPGA.io attribution in redistributed copies. The checksum identifies this file version; it does not approve a design.
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# FPGA I/O and power review worksheet
FPGA.io / KB Group Co.,LTD · Version 1.0 · 2026-09-29
Complete this worksheet from the exact device/package pinout and the implemented design. Blank cells are unresolved checks, not zero requirements.
## Identity
- Full MPN / package / grade:
- Schematic revision and date:
- Pinout document and revision:
- Electrical data sheet and revision:
- Tool release / device support:
## I/O bank allocation
| Signal group | Count | Direction | I/O standard | Bank supply | Clock / special pins | Pinout evidence |
|---|---|---|---|---|---|---|
| | | | | | | |
Check dedicated configuration pins, clock-capable pins, differential pairs, bank restrictions and reserved signals before counting spare pins. A package I/O total alone is not a valid bank allocation.
## Power rails
| Rail | Required voltage / tolerance | Estimated current | Estimation method / assumptions | Sequence | Regulator / distribution notes |
|---|---|---|---|---|---|
| | | | | | |
Use vendor power tools with actual activity, clocking, resources and temperature assumptions. A generic resource count cannot establish board current or thermal performance. Keep regulator input range, startup, decoupling and distribution analysis as separate checks.
## Bring-up observations to plan
| Observation | Measurement point | Instrument / setup | Acceptance criterion + source | Result |
|---|---|---|---|---|
| Rail ramp and sequence | | | | |
| Reset / configuration status | | | | |
| Reference clocks | | | | |
| Programming access | | | | |
| Interface activity | | | | |
| Temperature under defined workload | | | | |
Record instrumentation bandwidth and probe loading where relevant. Do not infer timing closure or signal integrity from an LED or successful programming alone.
## Review outcome
- Open issues and responsible person:
- Required schematic / constraints / layout changes:
- Conditions for moving to assembly:
Related planning tools: https://fpga.io/design-tools/io-budget/ and https://fpga.io/design-tools/power-rails/ . These organize inputs; the manufacturer's constraints remain authoritative.
Permission: copy and adapt this FPGA.io worksheet for internal or commercial engineering work; retain this attribution in redistributed copies. No third-party manufacturer documents are included. This planning aid does not approve a circuit or establish compliance.
Copy and adapt for internal or commercial engineering work. Retain FPGA.io attribution in redistributed copies. The checksum identifies this file version; it does not approve a design.
Copy and adapt for internal or commercial engineering work. Retain FPGA.io attribution in redistributed copies. The checksum identifies this file version; it does not approve a design.
Inspection, programming and functional-test boundaries
Release gate and approval references
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# FPGA board manufacturing handoff
FPGA.io / KB Group Co.,LTD · Version 1.0 · 2026-09-29
Use one revision-controlled package for quotation and engineering review. This checklist does not state that a manufacturing capability or test service has been accepted.
## Project scope
- Project / PCB revision / assembly revision:
- Quantity and delivery schedule:
- PCB only / assembly only / sourcing plus assembly:
- Technical and purchasing contacts:
- Required inspection and documentation:
## File register
| Deliverable | Filename / revision | Included? | Owner | Open issue |
|---|---|---|---|---|
| Fabrication data and board outline | | | | |
| Stack-up and material requirements | | | | |
| Impedance requirements and applicable nets | | | | |
| Drill / via specification | | | | |
| BOM with exact manufacturer ordering codes | | | | |
| Centroid / placement data and coordinate convention | | | | |
| Assembly drawings and polarity markings | | | | |
| Programming files and release identification | | | | |
| Test procedure / fixture / acceptance criteria | | | | |
## Component and BGA review
- Approved alternates and named approval authority:
- Customer-supplied material, quantity and packing:
- Package drawings, land patterns and pin/ball maps:
- Moisture sensitivity / storage / handling requirements from supplier documentation:
- Assembly constraints and rework expectations:
- Traceability and inspection records requested:
## Test boundaries
| Requested check | Equipment / fixture responsibility | Acceptance criterion | Quoted / pending confirmation |
|---|---|---|---|
| Electrical / continuity | | | |
| Assembly inspection | | | |
| Programming | | | |
| Functional test | | | |
Distinguish inspection, programming and functional testing. An assembly quote does not automatically include a fixture, application firmware, environmental qualification or full functional coverage.
## Release gate
- All files refer to the same approved revision:
- Open engineering questions resolved by:
- Written sourcing / fabrication / assembly / test scope agreed:
- Approval reference and date:
Project preparation: https://fpga.io/engineering/
Manufacturing scope: https://fpga.io/pcba-bga-assembly/
Quotation: https://fpga.io/rfq/
Do not put confidential Gerber/BOM files or credentials into public forum questions.
Permission: copy and adapt this FPGA.io worksheet for internal or commercial engineering work; retain this attribution in redistributed copies. No third-party manufacturer documents are included. This checklist does not replace engineering release or a project-specific manufacturing agreement.
Copy and adapt for internal or commercial engineering work. Retain FPGA.io attribution in redistributed copies. The checksum identifies this file version; it does not approve a design.
Copy and adapt for internal or commercial engineering work. Retain FPGA.io attribution in redistributed copies. The checksum identifies this file version; it does not approve a design.
Start with the complete manufacturer part number. Device pages connect specifications to applicable original documents; the files above are FPGA.io planning resources.
Planned directions. New files enter the library only when their contents, examples and usage conditions are ready.
Device & lifecycle evidencePlanned
Ordering-code records, package/grade differences and migration evidence.
Interfaces, timing & powerPlanned
Interface budgets, clock checks and measured power records.
PCB & high-speed layoutPlanned
Stack-up briefs, BGA escape and impedance / routing review.
Assembly & testPlanned
Traceability, programming, DFT and acceptance records.
RTL & verificationPlanned
Reproducible examples, testbenches and versioned run instructions.
Industry project briefsPlanned
Application-specific inputs for servers, base stations and instruments.
USE / ADAPT / REVIEW
Keep the evidence with the work.
These resources were prepared with AI assistance. Workbooks use fictional examples; planning files do not replace manufacturer specifications or project engineering approval.
Turn the file into a project record.
Keep a working copy with your project and revision.
Replace example inputs and record the sources behind your assumptions.
Review unresolved issues before a device or manufacturing decision.
