How this works
Total = single-ended signals + 2 × differential pairs + additional clock pins + reserved user I/O.
FPGA selection / T005
User I/O budget
Add single-ended signals, differential pairs, clocks and reserved user I/O.
Browser-local calculations Your inputs are processed on this device.Visible methods & limits Check assumptions before using a result.Explicit sharing Send a project only after reviewing the RFQ.
01 / DEFINE THE REQUIREMENT
Design inputs
02 / REVIEW THE OUTPUT
Your result
Ready for an example run. Check the inputs, then run the tool.
Total user-I/O demand with allocation checks
- Confirm the values and units.
- Run the check to generate your output.
- Review limitations before exporting or sharing.
Calculation & record
Review before use
The report records the tool version and calculation time. Project enquiry opens a separate form for your review; it does not submit automatically.
03 / METHOD & VERIFICATION
Understand the result.
Method version 1 · 2026-09-27
FPGA.io planning aid. Arithmetic and checklist output do not replace device documentation, a design tool or engineering approval.
Inputs and limits
Each count: whole number 0–1,000,000. Put each signal in only one category. Differential clocks belong in the pair count.
Verification example
32 single-ended + 8 differential pairs + 2 extra clock pins + 6 reserved → 56 user I/O.
Use the example inputs to inspect how the method behaves. This is a reference calculation, not a hardware test.
Follow a worked example + editable workbook →Data handling & review
Calculations and pasted lists stay in this browser. No account is required. An enquiry brief is stored temporarily in this tab's session only when you choose to transfer it.
Report a method or input issue →04 / CONTINUE THE TASK
Take the next useful step.
Keep exact device and board revisions with the assumptions you just checked.