FPGA.io / ENGINEERING COMMUNITY
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THE DISCUSSION BOARD
Recent engineering questions
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Ask the first question in this area →RECOMMENDED TOPICS
Questions engineers work on.
Editorial discussion starters—not a popularity ranking or existing user posts. Choose one to prepare your own question.
Device selection & alternativesChoosing an FPGA for a new design
Which logic, memory, I/O and lifecycle requirements actually eliminate a candidate?
Bring the exact device, tool release, relevant reports and what you have already tried.
Start with this question →Explore related resources →Device selection & alternativesReplacing a legacy FPGA
How do package, voltage, toolchain and bitstream changes affect a migration?
Bring the exact device, tool release, relevant reports and what you have already tried.
Start with this question →Explore related resources →Timing closure & CDCA practical timing-closure checklist
What do failing paths, constraints and implementation reports tell you to change?
Bring the exact device, tool release, relevant reports and what you have already tried.
Start with this question →Explore related resources →Timing closure & CDCClock-domain crossing and reset release
How will you verify synchronizers, data transfer and reset deassertion?
Bring the exact device, tool release, relevant reports and what you have already tried.
Start with this question →Explore related resources →RTL & verificationBuilding a useful RTL testbench
Which corner cases, assertions and reproducible stimuli belong in the first test?
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Start with this question →Explore related resources →RTL & verificationSimulation passes, hardware fails
Which assumptions about reset, timing, initialization and interfaces differ?
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Start with this question →Explore related resources →Vivado, Vitis & QuartusVivado or Quartus version migration
What device support, IP versions and build settings need to be retained?
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Start with this question →Explore related resources →Vivado, Vitis & QuartusZynq boot and hardware/software handoff
Where does boot stop, and which board, image and tool revisions reproduce it?
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Start with this question →Explore related resources →AXI, PCIe & EthernetDebugging AXI handshakes and stalls
What happens to VALID, READY, burst boundaries and backpressure?
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Start with this question →Explore related resources →AXI, PCIe & EthernetPCIe link training and throughput
Which lane configuration, reference clock and host evidence are available?
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Start with this question →Explore related resources →DDR, HBM & memoryDDR initialization and calibration
How will you isolate pin mapping, timing, termination and calibration failures?
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Start with this question →Explore related resources →DDR, HBM & memorySizing buffers for a streaming design
What burst length, stall time and clock mismatch must the buffer absorb?
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Start with this question →Explore related resources →PCB, BGA & signal integrityBGA fanout and stackup choices
How do pitch, via strategy, return paths and fabrication constraints interact?
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Start with this question →Explore related resources →PCB, BGA & signal integrityI/O banks, voltages and pin allocation
Can the exact package satisfy the signal groups and bank-voltage rules?
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Start with this question →Explore related resources →Power, clocks & resetPower rails, sequencing and margin
Which currents are assumptions, and what evidence is needed for regulators and sequencing?
Bring the exact device, tool release, relevant reports and what you have already tried.
Start with this question →Explore related resources →Bring-up, JTAG & debugA first-power and JTAG debug plan
What safe measurements distinguish power, reset, clock and configuration faults?
Bring the exact device, tool release, relevant reports and what you have already tried.
Start with this question →Explore related resources →Servers, instruments & applicationsFPGA pipelines for instruments and servers
How do latency, bandwidth, precision and host interfaces shape the architecture?
Bring the exact device, tool release, relevant reports and what you have already tried.
Start with this question →Explore related resources →Assembly, programming & testProgramming and testing an FPGA board
Which image version, serial record and acceptance evidence should travel with each board?
Bring the exact device, tool release, relevant reports and what you have already tried.
Start with this question →Explore related resources →Topic selection draws on established engineering tasks, including Altera design support and AMD performance and timing guidance. These sources do not endorse this community.
A USEFUL TECHNICAL EXCHANGE
Context makes an answer better.
- Give the full device, board revision and tool version.
- Separate expected behavior from observed results.
- Explain the smallest reproducible case and checks already made.
- Link to public source documents; label assumptions and AI assistance.
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Discussion standards
- Separate measured results, source information and assumptions.
- Keep replies constructive and disclose commercial interests.
- Identify AI-assisted answers; do not claim tests or expertise that did not occur.
- A suggested alternative requires its own engineering checks.