Read an exact FPGA ordering code
Keep package, speed and temperature grade attached to the part you are evaluating.
Device selectionRead & apply →
FPGA.io / PRACTICAL ENGINEERING
FPGA tutorials.
Learn with a task in hand.
Read an exact part number, work through a resource budget or prepare a board review. Leave with a calculation, a checklist or a better engineering question.
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AVAILABLE TO READ
Choose a guide or work through an example.
Foundation explains the decision. Applied connects it to a board or manufacturing review.
6 of 6 learning items shown
Reset filtersBuild an I/O and memory budget
Turn signal and buffer requirements into explicit resource assumptions.
I/O & memoryRead & apply →
Prepare a board for engineering review
Bring power assumptions, package evidence and manufacturing revisions into one review.
PCB & PCBA handoffRead & apply →
Work through an 82-pin I/O budget
Count single-ended signals, differential pairs, clocks and spare I/O without double counting.
I/O & memoryRead & apply →
Build a 5.40 W input-power budget
Follow conversion losses and a 20% input margin from two assumed power rails.
Power planningRead & apply →
Find a revision mismatch before assembly
Review a file pack whose PCB and BOM disagree with its placement-file revision.
PCB & PCBA handoffRead & apply →
No available item matches those filters.
Clear a filter or explore the planned learning tracks below. Planned topics do not have empty article pages.
View the learning roadmap →READ / CHECK / APPLY
A useful output at each step.
FOUNDATION / DEVICE SELECTION
Read an exact FPGA ordering code
Outcome: a traceable shortlist that retains the package, speed and temperature grade.
- Before you start
- The full BOM ordering code and its manufacturer documents.
- What you will produce
- A traceable device shortlist with unresolved compatibility checks.
Work through the decision
- Start with the complete manufacturer code from the BOM. A family name or base device is not a purchasable ordering code.
- Use manufacturer ordering information to check the package and grade. Keep the document revision with your record.
- Check package-specific I/O and serial resources. Compare alternatives only after pinout, bank voltage and tool support are reviewed.
Your working output
Save the exact code, applicable documents and unresolved compatibility checks in a selection brief.
Apply it to your project
CHECK YOUR DECISION
Read the reasoning
Start with the complete ordering code. Then confirm package, grade, pinout and the applicable document revision; neither a family name nor a ball count establishes compatibility.
FOUNDATION / DESIGN PLANNING
Build an I/O and memory budget
Outcome: explicit signal and buffer requirements before you select a device/package.
- Before you start
- An interface list, signal directions, memory width and depth.
- What you will produce
- An I/O allocation and memory requirement ready for device-specific review.
Work through the decision
- Group signals by interface, direction and I/O standard. Identify configuration, clock and dedicated pins separately.
- Record buffer depth, width and access pattern. Distinguish a raw bit requirement from how it maps to actual memory blocks.
- Use the I/O and BRAM planning tools, then validate bank allocation and resource mapping in the selected vendor toolchain.
Your working output
Keep assumptions, units and spare capacity visible. Native logic and DSP counts from different architectures are not equivalent.
Apply it to your project
CHECK YOUR DECISION
Read the reasoning
Architecture-specific logic and DSP definitions differ. Preserve the native definitions and validate the implementation in the selected toolchain.
PRACTICE / BOARD HANDOFF
Prepare a board for engineering review
Outcome: a consistent input package for power, layout, sourcing and assembly review.
- Before you start
- Exact device/package, rail estimates and current board-file revisions.
- What you will produce
- A project review brief with open decisions and named owners.
Work through the decision
- Record each power rail, its source requirement and the method used for estimating current. Tie estimates to clocks, activity and temperature assumptions.
- Check the package drawing, footprint, pin/ball map and routing constraints against the exact device. A matching ball count is not proof of compatibility.
- Align the BOM, PCB, assembly and programming revisions. Define inspection and functional-test scope separately before requesting a build.
Your working output
List open decisions and named owners. A checklist organizes the review; it does not replace timing, power or manufacturing validation.
Apply it to your project
CHECK YOUR DECISION
Read the reasoning
A useful handoff records the actual revision, source evidence and open review items. Inspection, programming and functional-test requirements need their own agreed scope.
THREE WORKED EXAMPLES
Follow the numbers. Keep the assumptions.
Original FPGA.io planning exercises · 30 September 2026. Fictional inputs, not measured device performance. Each workbook includes a blank Template and a filled Example.
01 / I/O PLANNING
Does an 82-pin budget fit the package?
- Before you start
- The fictional signal list below; no hardware is required.
- What you will produce
- An 82-pin calculation plus a package/bank verification checklist.
A signal total starts a package review; it cannot finish it.
| Requirement | Count | Signal pins |
|---|---|---|
| Single-ended signals | 32 | 32 |
| Differential pairs | 16 pairs | 32 |
| Other clock pins | 2 | 2 |
| Spare signal pins | 16 | 16 |
32 + (2 × 16) + 2 + 16 = 82 signal pins. Count each signal once. Dedicated power, ground and configuration pins are outside this calculation.
- Open the I/O tool and enter these four counts; the result should be 82.
- Set single-ended signals to 0: the result becomes 50. A blank input is unknown, not zero.
- Map each interface to a bank, I/O standard, voltage and clock/pair constraint using the exact package pinout.
Decision gate: do not approve a package from a family maximum I/O figure. In the XC7A100T-1CSG324C document example, first establish the package-specific resources; this exercise does not assert that the example design fits that device.
CHECK YOUR DECISION
Read the reasoning
The arithmetic only establishes demand. Check the exact package pinout, bank voltages, differential pairs, clocks and reserved/dedicated pins before deciding it fits.
02 / POWER PLANNING
From 3.80 W of load to a 5.40 W input budget.
- Before you start
- Two fictional rail assumptions and converter efficiencies.
- What you will produce
- A reproducible 3.80 W load / 4.50 W input / 5.40 W margin budget.
Efficiency and reserve belong to the input estimate; they do not predict FPGA current.
| Assumed rail | Load V × A | Efficiency | Input power |
|---|---|---|---|
| Rail 1 | 1.0 V × 2.0 A = 2.00 W | 80% | 2.00 / 0.80 = 2.50 W |
| Rail 2 | 1.8 V × 1.0 A = 1.80 W | 90% | 1.80 / 0.90 = 2.00 W |
Input: 2.50 + 2.00 = 4.50 W.
20% input margin: 4.50 × 1.20 = 5.40 W.
- Enter the two rows in the power planner as
Rail 1, 1, 2, 80andRail 2, 1.8, 1, 90; set margin to 20. - Compare the tool output with the filled workbook. In the workbook, efficiency cells use percentage formatting: enter 80%, not 80.
- Replace assumptions with vendor-estimator results tied to activity, clocks and temperature; retain the estimator version and report.
Decision gate: review sequencing, transient current, regulator limits, decoupling and thermal behavior separately. This arithmetic does not approve a regulator or power tree.
CHECK YOUR DECISION
Read the reasoning
4.50 × 1.20 = 5.40 W. The input estimate already includes conversion losses. Current assumptions, transients, sequencing and thermal behavior still require separate validation.
03 / MANUFACTURING HANDOFF
Find the revision mismatch before assembly.
- Before you start
- The fictional Rev B PCB/BOM and Rev A placement record below.
- What you will produce
- A handoff action list with revision and test-scope decisions.
An otherwise complete file pack can still describe two different boards.
| File or decision | Fictional example | Action |
|---|---|---|
| PCB + BOM | Rev B | Confirm approved revision |
| Placement / CPL | Rev A | Stop: re-export against Rev B |
| U1 alternate | Awaiting approval | Retain exact MPN until approved |
| Functional test | Fixture not defined | Agree acceptance criteria and responsibility |
- Use one board revision across the fabrication, BOM and placement files. Name an owner for every unresolved item.
- Separate inspection from functional test. Do not assume an assembly quote includes programming, fixtures or a test procedure.
- Resolve the placement mismatch, then prepare a brief with quantity, destination, requested date and agreed review scope.
Ready for review ≠ approved for manufacture. The workbook is an editable handoff checklist, not a supplier acceptance certificate.
CHECK YOUR DECISION
Read the reasoning
File presence is not revision consistency. Re-export and check the placement data against the approved board revision, then resolve alternates and test responsibilities.
PLANNED LEARNING TRACKS
Build depth one verified task at a time.
These are future editorial directions, not published courses. Each lesson needs a reproducible output and its own review before release.
RTL & simulationPlanned
Reset controllers, self-checking testbenches, finite-state machines and ready-valid pipelines.
Required learning output: A minimal design, runnable testbench and explicit tool version.
Clocking & timingPlanned
Clock constraints, single-bit CDC, reset-domain crossing and timing-closure investigations.
Required learning output: Timing assumptions, constraint scope and reproducible reports.
Memory & interfacesPlanned
BRAM organization, synchronous/asynchronous FIFOs, DDR integration and AXI interfaces.
Required learning output: Throughput/latency requirements and an implementation check.
DSP & data pathsPlanned
Fixed-point arithmetic, FIR filters, FFT streaming and image line buffers.
Required learning output: A numerical reference and quantified error/throughput boundaries.
Devices & design platformsPlanned
Artix-7 bring-up, exact-device selection and vendor-tool workflows.
Required learning output: Applicable manufacturer documents and a clearly identified platform.
PCB, power & manufacturingPlanned
I/O banks, rail planning, package escape, programming and board handoff.
Required learning output: A design-review worksheet and confirmed manufacturing assumptions.
EDITORIAL SCOPE
Understand what has been checked.
FPGA.io editorial resources · AI-assisted preparation. These guides explain planning decisions. Worked examples use fictional inputs and do not claim hardware validation or manufacturer endorsement.
Use the source that matches the decision.
Keep the exact ordering code, document revision, tool release and operating conditions with your work. Device-specific specifications belong to the linked manufacturer documents; arithmetic alone cannot approve a component or board.