# FPGA I/O and power review worksheet
FPGA.io / KB Group Co.,LTD · Version 1.0 · 2026-09-29

Complete this worksheet from the exact device/package pinout and the implemented design. Blank cells are unresolved checks, not zero requirements.

## Identity
- Full MPN / package / grade:
- Schematic revision and date:
- Pinout document and revision:
- Electrical data sheet and revision:
- Tool release / device support:

## I/O bank allocation
| Signal group | Count | Direction | I/O standard | Bank supply | Clock / special pins | Pinout evidence |
|---|---|---|---|---|---|---|
| | | | | | | |

Check dedicated configuration pins, clock-capable pins, differential pairs, bank restrictions and reserved signals before counting spare pins. A package I/O total alone is not a valid bank allocation.

## Power rails
| Rail | Required voltage / tolerance | Estimated current | Estimation method / assumptions | Sequence | Regulator / distribution notes |
|---|---|---|---|---|---|
| | | | | | |

Use vendor power tools with actual activity, clocking, resources and temperature assumptions. A generic resource count cannot establish board current or thermal performance. Keep regulator input range, startup, decoupling and distribution analysis as separate checks.

## Bring-up observations to plan
| Observation | Measurement point | Instrument / setup | Acceptance criterion + source | Result |
|---|---|---|---|---|
| Rail ramp and sequence | | | | |
| Reset / configuration status | | | | |
| Reference clocks | | | | |
| Programming access | | | | |
| Interface activity | | | | |
| Temperature under defined workload | | | | |

Record instrumentation bandwidth and probe loading where relevant. Do not infer timing closure or signal integrity from an LED or successful programming alone.

## Review outcome
- Open issues and responsible person:
- Required schematic / constraints / layout changes:
- Conditions for moving to assembly:

Related planning tools: https://fpga.io/design-tools/io-budget/ and https://fpga.io/design-tools/power-rails/ . These organize inputs; the manufacturer's constraints remain authoritative.

Permission: copy and adapt this FPGA.io worksheet for internal or commercial engineering work; retain this attribution in redistributed copies. No third-party manufacturer documents are included. This planning aid does not approve a circuit or establish compliance.