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XC2S50

Spartan-II base device for legacy design maintenance. Package, speed and temperature suffixes are required to identify an orderable part.

FPGA.io Part Number FIO-96C7AF95F2D3B476Internal catalogue reference · manufacturer MPN remains unchanged

Technical reference · Base device — ordering suffix not specified · Checked 2026-09-28

XC2S50 — technical feature overview
Technical schematicFPGA.io technical schematic for XC2S50. Values summarize the documented fields below; consult their source conditions. This is an abstract diagram, not a product photograph, package drawing or pinout. Parameter sources below ↓

DOCUMENTED FACTS

Technical parameters

6 source-linked fields

Values apply to the device and conditions identified in each source. Family maxima, package limits and full ordering-code specifications must not be treated as interchangeable.

ParameterDocumented valueSource & conditions
Logic cells1728 cellsSpartan-II FPGA Family Data Sheet, v2.9 (2021-03-12) ↗Table 1, p. 2, XC2S50 row
Configurable logic blocks384 CLBsSpartan-II FPGA Family Data Sheet, v2.9 (2021-03-12) ↗Table 1, p. 2, XC2S50 row
Block RAM32 Kbit (1024 bits)Spartan-II FPGA Family Data Sheet, v2.9 (2021-03-12) ↗Table 1, p. 2, XC2S50 row
Distributed RAM24576 bitsSpartan-II FPGA Family Data Sheet, v2.9 (2021-03-12) ↗Table 1, p. 2, XC2S50 row
Delay-locked loops4 DLLsSpartan-II FPGA Family Data Sheet, v2.9 (2021-03-12) ↗Table 1, p. 2, XC2S50 row; Features on same page
Maximum user I/O176 pinsSpartan-II FPGA Family Data Sheet, v2.9 (2021-03-12) ↗Table 1, p. 2, XC2S50 row; excludes four global clock/user-input pins; package dependent

Official documents

Spartan-II FPGA Family Data Sheet, v2.9 (2021-03-12)Table 1, p. 2; Table 2, p. 4; Ordering Information, p. 5PDF ↗Legacy FPGA and CPLD Product Discontinuation Notice, v1.1 (2024-01-29)Scope, p. 1; Table 3, p. 2; Table 5, pp. 3-5; final-order and final-delivery dates, p. 5PDF ↗

Ordering and board constraints

This reference identifies a base device. Package, speed grade, temperature, qualification and packing suffixes have not been inferred.

  • Check the original 2.5 V core supply and package-specific I/O chart.
  • Preserve the earlier ISE build environment and external configuration design.
  • Confirm current availability and lifecycle for the complete code before procurement.
  • Review pinout, electrical conditions and the exact document revision before PCB release.

Prepare a complete request

Include the full ordering code, quantity, delivery requirement and traceability needs. For an assembled board, include BOM revision, programming and test scope.

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Series & categories

COMPLETE PART IDENTITIES

Ordering numbers for XC2S50

3 documented codes

These references belong to this device. Evidence labels distinguish reviewed specifications, public listings and manufacturer coding examples. Counts describe this site’s documented coverage, not stock or all configurations offered by the manufacturer.

Full ordering numberPackageSpeed / temperatureEvidenceNext step
XC2S50-5PQ208CNot verifiedNot verifiedNot verifiedDistributor-listed identityView source ↗Device details →Request quotation
XC2S50-5PQG208INot verifiedNot verifiedNot verifiedDistributor-listed identityView source ↗Device details →Request quotation
XC2S50-5TQG144CNot verifiedNot verifiedNot verifiedDistributor-listed identityView source ↗Device details →Request quotation

3 of 3 codes shown

Not verified means that parameter has not been independently established for this exact code. A code example is not confirmation that a configuration can be ordered today.

Other devices in this product line

Compare the documented requirements; inclusion in the same series does not establish interchangeability.

BASE DEVICE

XC2S200

Spartan-II base device for legacy design maintenance. Package, speed and temperature suffixes are required to identify an orderable part.

Logic cells
5292 cells
Configurable logic blocks
1176 CLBs
Block RAM
56 Kbit (1024 bits)
1 ordering codeXC2S200-5FGG456C →
Specifications & documents →

BASE DEVICE

XC2S600E

Spartan-IIE base device for legacy design maintenance. Package, speed and temperature suffixes are required to identify an orderable part.

Logic cells
15552 cells
Configurable logic blocks
3456 CLBs
Block RAM
288 Kbit (1024 bits)
0 ordering codesExact ordering-code evidence is still being collected.
Specifications & documents →

BASE DEVICE

XC3S200

Spartan-3 base device for legacy design maintenance. Package, speed and temperature suffixes are required to identify an orderable part.

Equivalent logic cells
4320 cells
Configurable logic blocks
480 CLBs
Block RAM
216 Kbit (1024 bits)
1 ordering codeXC3S200-4FTG256C →
Specifications & documents →