BASE DEVICE
XC2S50
Spartan-II base device for legacy design maintenance. Package, speed and temperature suffixes are required to identify an orderable part.
- Logic cells
- 1728 cells
- Configurable logic blocks
- 384 CLBs
- Block RAM
- 32 Kbit (1024 bits)
AMD / Xilinx / TECHNICAL REFERENCE
XC2S200
Spartan-II base device for legacy design maintenance. Package, speed and temperature suffixes are required to identify an orderable part.
FPGA.io Part Number FIO-381B909392A6177CInternal catalogue reference · manufacturer MPN remains unchanged
Technical reference · Base device — ordering suffix not specified · Checked 2026-09-28
DOCUMENTED FACTS
Technical parameters
Values apply to the device and conditions identified in each source. Family maxima, package limits and full ordering-code specifications must not be treated as interchangeable.
| Parameter | Documented value | Source & conditions |
|---|---|---|
| Logic cells | 5292 cells | Spartan-II FPGA Family Data Sheet, v2.9 (2021-03-12) ↗Table 1, p. 2, XC2S200 row |
| Configurable logic blocks | 1176 CLBs | Spartan-II FPGA Family Data Sheet, v2.9 (2021-03-12) ↗Table 1, p. 2, XC2S200 row |
| Block RAM | 56 Kbit (1024 bits) | Spartan-II FPGA Family Data Sheet, v2.9 (2021-03-12) ↗Table 1, p. 2, XC2S200 row |
| Distributed RAM | 75264 bits | Spartan-II FPGA Family Data Sheet, v2.9 (2021-03-12) ↗Table 1, p. 2, XC2S200 row |
| Delay-locked loops | 4 DLLs | Spartan-II FPGA Family Data Sheet, v2.9 (2021-03-12) ↗Table 1, p. 2, XC2S200 row; Features on same page |
| Maximum user I/O | 284 pins | Spartan-II FPGA Family Data Sheet, v2.9 (2021-03-12) ↗Table 1, p. 2, XC2S200 row; excludes four global clock/user-input pins; package dependent |
Official documents
Spartan-II FPGA Family Data Sheet, v2.9 (2021-03-12)Table 1, p. 2; Table 2, p. 4; Ordering Information, p. 5PDF ↗Legacy FPGA and CPLD Product Discontinuation Notice, v1.1 (2024-01-29)Scope, p. 1; Table 3, p. 2; Table 5, pp. 3-5; final-order and final-delivery dates, p. 5PDF ↗Ordering and board constraints
This reference identifies a base device. Package, speed grade, temperature, qualification and packing suffixes have not been inferred.
- Check the original 2.5 V core supply and package-specific I/O chart.
- Preserve the earlier ISE build environment and external configuration design.
- Confirm current availability and lifecycle for the complete code before procurement.
- Review pinout, electrical conditions and the exact document revision before PCB release.
Prepare a complete request
Include the full ordering code, quantity, delivery requirement and traceability needs. For an assembled board, include BOM revision, programming and test scope.
Request this device ↗Series & categories
COMPLETE PART IDENTITIES
Ordering numbers for XC2S200
These references belong to this device. Evidence labels distinguish reviewed specifications, public listings and manufacturer coding examples. Counts describe this site’s documented coverage, not stock or all configurations offered by the manufacturer.
| Full ordering number | Package | Speed / temperature | Evidence | Next step |
|---|---|---|---|---|
| XC2S200-5FGG456C | Not verified | Not verifiedNot verified | Distributor-listed identityView source ↗ | Device details →Request quotation |
1 of 1 codes shown
No ordering codes match. Clear the search to see this device’s documented codes.
Not verified means that parameter has not been independently established for this exact code. A code example is not confirmation that a configuration can be ordered today.
Other devices in this product line
Compare the documented requirements; inclusion in the same series does not establish interchangeability.
BASE DEVICE
XC2S100E
Spartan-IIE base device for legacy design maintenance. Package, speed and temperature suffixes are required to identify an orderable part.
- Logic cells
- 2700 cells
- Configurable logic blocks
- 600 CLBs
- Block RAM
- 40 Kbit (1024 bits)
2 ordering codesXC2S100E-6FTG256C →XC2S100E-6TQ144C →
Specifications & documents →BASE DEVICE
XC2S600E
Spartan-IIE base device for legacy design maintenance. Package, speed and temperature suffixes are required to identify an orderable part.
- Logic cells
- 15552 cells
- Configurable logic blocks
- 3456 CLBs
- Block RAM
- 288 Kbit (1024 bits)
0 ordering codesExact ordering-code evidence is still being collected.
Specifications & documents →BASE DEVICE
XC3S200
Spartan-3 base device for legacy design maintenance. Package, speed and temperature suffixes are required to identify an orderable part.
- Equivalent logic cells
- 4320 cells
- Configurable logic blocks
- 480 CLBs
- Block RAM
- 216 Kbit (1024 bits)
1 ordering codeXC3S200-4FTG256C →
Specifications & documents →BASE DEVICE
XC3S200A
Spartan-3A base device for legacy design maintenance. Package, speed and temperature suffixes are required to identify an orderable part.
- Equivalent logic cells
- 4032 cells
- Configurable logic blocks
- 448 CLBs
- Block RAM
- 288 Kbit (1024 bits)
2 ordering codesXC3S200A-4FT256C →XC3S200A-4VQG100C →
Specifications & documents →BASE DEVICE
XC3S200AN
Spartan-3AN base device for legacy design maintenance, with integrated configuration flash. Package, speed and temperature suffixes are required to identify an orderable part.
- Equivalent logic cells
- 4032 cells
- Configurable logic blocks
- 448 CLBs
- Block RAM
- 288 Kbit (1024 bits)