AMD / Xilinx / TECHNICAL REFERENCE

ZU28DR

Zynq UltraScale+ RFSoC base device in the documented generation.

FPGA.io Part Number FIO-4B43C0ECB7B9C1D4Internal catalogue reference · manufacturer MPN remains unchanged

Technical reference · Base device — ordering suffix not specified · Checked 2026-09-28

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ZU28DR — technical feature overview — Technical schematicFPGA.io technical schematic for ZU28DR. Values summarize the documented fields below; consult their source conditions. This is an abstract diagram, not a product photograph, package drawing or pinout. Parameter sources below ↓

DOCUMENTED FACTS

Technical parameters

3 source-linked fields

Values apply to the device and conditions identified in each source. Family maxima, package limits and full ordering-code specifications must not be treated as interchangeable.

Parameter	Documented value	Source & conditions
System logic cells	930 K	AMD Zynq UltraScale+ RFSoCs ↗Gen 1 / Gen 2 / Gen 3 / DFE Programmable Logic tables; ZU28DR column / System logic cells row
DSP slices	4272	AMD Zynq UltraScale+ RFSoCs ↗Gen 1 / Gen 2 / Gen 3 / DFE Programmable Logic tables; ZU28DR column / DSP slices row
Memory	60.5 Mb	AMD Zynq UltraScale+ RFSoCs ↗Gen 1 / Gen 2 / Gen 3 / DFE Programmable Logic tables; ZU28DR column / Memory row

Official documents

AMD Zynq UltraScale+ RFSoCsGen 1 / Gen 2 / Gen 3 / DFE Programmable Logic tablesWeb ↗

Ordering and board constraints

This reference identifies a base device. Package, speed grade, temperature, qualification and packing suffixes have not been inferred.

Base-device reference; select and verify the package, speed and temperature suffix separately.
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Series & categories

Zynq RFSoC Gen 1 →

COMPLETE PART IDENTITIES

Ordering numbers for ZU28DR

0 documented codes

These references belong to this device. Evidence labels distinguish reviewed specifications, public listings and manufacturer coding examples. Counts describe this site’s documented coverage, not stock or all configurations offered by the manufacturer.

Exact ordering code requires confirmation

This bounded review did not verify a literal full ordering code. This does not establish that no code exists. Package, speed and temperature matrices were not expanded.

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