FPGA COMPONENTS & BOARD MANUFACTURING For research, development & industrial systems

MANUFACTURER / PRODUCT & DEVELOPMENT GUIDE

Synopsys

Synopsys licenses semiconductor IP for interface, processing and other SoC functions. Its IP and EDA offerings are not standard packaged-chip inventory.

IP licensing: these are designs integrated into an ASIC or SoC, not standard packaged-chip MPNs.

Product & resource entries
8
Portfolio groups
1
Reviewed FPGA MPNs
0
Source review

0 device refs · 0 ordering codes Counts cover published site records, including subcategories. They do not describe stock or the manufacturer’s complete catalogue.

PRODUCT ARCHITECTURE

Product families & categories

Source-reviewed category map
Portfolio scope & source review

Official DesignWare navigation reviewed for interface, ARC processor and security IP. Processor IP is a licensable core, security includes root-of-trust and cryptography, and broad interface IP covers multiple protocols; specific process-node IP requires vendor validation.

Clear filters

3 matching product lines · browse subseries within each family

Product lines

ARC processors

ARC processors is a product-line reference within Synopsys. Use the manufacturer source to confirm the exact device or deliverable and its current support status.

0 device refs · 0 ordering codesExplore ARC processors →

DEVELOPMENT ECOSYSTEM

Development resources

Use the manufacturer’s current device-support list and release documentation to confirm compatibility.

FROM SELECTION TO PRODUCTION

Turn a product choice into a board requirement.

Confirm the exact device, then connect sourcing, board preparation and assembly review in one project.

Engineering checkpoints

  • Confirm licensing, target process or host architecture, integration deliverables and verification responsibilities.
  • An IP licence is not a packaged IC; distinguish design-service, licence and silicon procurement scopes.
  • Confirm the protocol revision, data rate, logic level, channel count and termination requirements.
  • Review signal integrity, isolation where applicable, clocking and package pinout before substitution.
  • Select the instruction set, operating-system/BSP support, boot flow and memory interface for the target application.
Use our engineering worksheets →

TRACEABLE INFORMATION

Sources & identity

Official DesignWare navigation reviewed for interface, ARC processor and security IP. Processor IP is a licensable core, security includes root-of-trust and cryptography, and broad interface IP covers multiple protocols; specific process-node IP requires vendor validation.

Checked 2026-09-28. Manufacturer names and images belong to their owners. Listing does not imply stock or an authorized distribution relationship.

Also searchable as: 新思科技 · DesignWare · ARC

Official and identified references

Each product page links its own portfolio evidence. Exact device specifications and lifecycle notices take precedence over family-level summaries.

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