Eastsoft / 东软载波微电子 / TECHNICAL REFERENCE

ES32F3654LT

ES32F3654 microcontroller variant explicitly listed in the manufacturer's datasheet.

FPGA.io Part Number FIO-A616CB2146F7472EInternal catalogue reference · manufacturer MPN remains unchanged

Technical reference · Base device — ordering suffix not specified · Checked 2026-09-28

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ES32F3654LT — technical feature overview — Technical schematicFPGA.io technical schematic for ES32F3654LT. Values summarize the documented fields below; consult their source conditions. This is an abstract diagram, not a product photograph, package drawing or pinout. Parameter sources below ↓

DOCUMENTED FACTS

Technical parameters

4 source-linked fields

Values apply to the device and conditions identified in each source. Family maxima, package limits and full ordering-code specifications must not be treated as interchangeable.

Parameter	Documented value	Source & conditions
CPU core	Arm Cortex-M3	ES32F3656/655/654/653/651 datasheet V1.7 ↗p. 2 Features and product-code list
Maximum CPU frequency	72 MHz	ES32F3656/655/654/653/651 datasheet V1.7 ↗p. 2 Features and product-code list
Operating supply	2.6 to 5.5 V	ES32F3656/655/654/653/651 datasheet V1.7 ↗p. 2 Features and product-code list
CAN interface	CAN 2.0B	ES32F3656/655/654/653/651 datasheet V1.7 ↗p. 2 Features and product-code list

Official documents

ES32F3656/655/654/653/651 datasheet V1.7p. 2 Features and product-code listPDF ↗

Ordering and board constraints

This reference identifies a base device. Package, speed grade, temperature, qualification and packing suffixes have not been inferred.

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Series & categories

Microcontrollers →

COMPLETE PART IDENTITIES

Ordering numbers for ES32F3654LT

0 documented codes

These references belong to this device. Evidence labels distinguish reviewed specifications, public listings and manufacturer coding examples. Counts describe this site’s documented coverage, not stock or all configurations offered by the manufacturer.

Exact ordering code requires confirmation

The cited public material did not establish a literal complete ordering row in this pass. This is an evidence limit, not a claim that no code exists. The existing device identity is retained; no suffix combinations, neighboring chips, boards or systems are substituted.

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