BASE DEVICE
PH1P100
SALPHOENIX 1P FPGA base device with an integrated RISC-V MCU.
- RISC-V MCU frequency
- 300 MHz
- MIPI D-PHY interfaces
- 2 interfaces
- SERDES line rate
- 12.5 Gbps
Anlogic / 安路科技 / TECHNICAL REFERENCE
SALPHOENIX 1P FPGA base device with an integrated RISC-V MCU.
FPGA.io Part Number FIO-DE6A71F99941BB32Internal catalogue reference · manufacturer MPN remains unchanged
Technical reference · Base device — ordering suffix not specified · Checked 2026-09-28
DOCUMENTED FACTS
Values apply to the device and conditions identified in each source. Family maxima, package limits and full ordering-code specifications must not be treated as interchangeable.
| Parameter | Documented value | Source & conditions |
|---|---|---|
| RISC-V MCU frequency | 300 MHz | Anlogic: Two New Mass-Production Families ↗24 June 2026; SALPHOENIX 1P PH1P50 and PH1P100 section; PH1P50 column / RISC-V MCU frequency row |
| MIPI D-PHY interfaces | 2 interfaces | Anlogic: Two New Mass-Production Families ↗24 June 2026; SALPHOENIX 1P PH1P50 and PH1P100 section; PH1P50 column / MIPI D-PHY interfaces row |
| SERDES line rate | 12.5 Gbps | Anlogic: Two New Mass-Production Families ↗24 June 2026; SALPHOENIX 1P PH1P50 and PH1P100 section; PH1P50 column / SERDES line rate row |
| PCI Express support | Gen3 ×4 | Anlogic: Two New Mass-Production Families ↗24 June 2026; SALPHOENIX 1P PH1P50 and PH1P100 section; PH1P50 column / PCI Express support row |
This reference identifies a base device. Package, speed grade, temperature, qualification and packing suffixes have not been inferred.
Include the full ordering code, quantity, delivery requirement and traceability needs. For an assembled board, include BOM revision, programming and test scope.
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These references belong to this device. Evidence labels distinguish reviewed specifications, public listings and manufacturer coding examples. Counts describe this site’s documented coverage, not stock or all configurations offered by the manufacturer.
This bounded review did not verify a literal full ordering code. This does not establish that no code exists. Package, speed and temperature matrices were not expanded.
Request an exact-code review →Compare the documented requirements; inclusion in the same series does not establish interchangeability.
BASE DEVICE
SALPHOENIX 1P FPGA base device with an integrated RISC-V MCU.