FPGA COMPONENTS & BOARD MANUFACTURING For research, development & industrial systems

Anlogic / 安路科技 / TECHNICAL REFERENCE

PH1P50

SALPHOENIX 1P FPGA base device with an integrated RISC-V MCU.

FPGA.io Part Number FIO-DE6A71F99941BB32Internal catalogue reference · manufacturer MPN remains unchanged

Technical reference · Base device — ordering suffix not specified · Checked 2026-09-28

PH1P50 — technical feature overview
Technical schematicFPGA.io technical schematic for PH1P50. Values summarize the documented fields below; consult their source conditions. This is an abstract diagram, not a product photograph, package drawing or pinout. Parameter sources below ↓

DOCUMENTED FACTS

Technical parameters

4 source-linked fields

Values apply to the device and conditions identified in each source. Family maxima, package limits and full ordering-code specifications must not be treated as interchangeable.

ParameterDocumented valueSource & conditions
RISC-V MCU frequency300 MHzAnlogic: Two New Mass-Production Families ↗24 June 2026; SALPHOENIX 1P PH1P50 and PH1P100 section; PH1P50 column / RISC-V MCU frequency row
MIPI D-PHY interfaces2 interfacesAnlogic: Two New Mass-Production Families ↗24 June 2026; SALPHOENIX 1P PH1P50 and PH1P100 section; PH1P50 column / MIPI D-PHY interfaces row
SERDES line rate12.5 GbpsAnlogic: Two New Mass-Production Families ↗24 June 2026; SALPHOENIX 1P PH1P50 and PH1P100 section; PH1P50 column / SERDES line rate row
PCI Express supportGen3 ×4Anlogic: Two New Mass-Production Families ↗24 June 2026; SALPHOENIX 1P PH1P50 and PH1P100 section; PH1P50 column / PCI Express support row

Official documents

Anlogic: Two New Mass-Production Families24 June 2026; SALPHOENIX 1P PH1P50 and PH1P100 sectionWeb ↗

Ordering and board constraints

This reference identifies a base device. Package, speed grade, temperature, qualification and packing suffixes have not been inferred.

  • Base-device reference; select and verify the package, speed and temperature suffix separately.
  • These are device-family capabilities stated for PH1P50 and PH1P100; confirm package-specific lane and I/O availability.
  • Confirm current availability and lifecycle for the complete code before procurement.
  • Review pinout, electrical conditions and the exact document revision before PCB release.

Prepare a complete request

Include the full ordering code, quantity, delivery requirement and traceability needs. For an assembled board, include BOM revision, programming and test scope.

Request this device ↗

Discuss sourcing + PCBA →

Series & categories

COMPLETE PART IDENTITIES

Ordering numbers for PH1P50

0 documented codes

These references belong to this device. Evidence labels distinguish reviewed specifications, public listings and manufacturer coding examples. Counts describe this site’s documented coverage, not stock or all configurations offered by the manufacturer.

Exact ordering code requires confirmation

This bounded review did not verify a literal full ordering code. This does not establish that no code exists. Package, speed and temperature matrices were not expanded.

Ordering identity reference ↗

Request an exact-code review →

Other devices in this product line

Compare the documented requirements; inclusion in the same series does not establish interchangeability.

BASE DEVICE

PH1P100

SALPHOENIX 1P FPGA base device with an integrated RISC-V MCU.

RISC-V MCU frequency
300 MHz
MIPI D-PHY interfaces
2 interfaces
SERDES line rate
12.5 Gbps
0 ordering codesExact ordering-code evidence is still being collected.
Specifications & documents →