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Choosing a Gowin FPGA: LittleBee, Arora II and Arora V
FPGA.io editorial · AI-assisted preparation and review; not human engineering certification.
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Choosing a Gowin FPGA starts with the signals and constraints your board must satisfy, not the largest logic count in a family table. This guide produces a shortlist and a list of unresolved checks. It does not establish pin compatibility, current stock, tool licensing or timing closure for a particular ordering code.
Use it before committing the schematic or requesting a quote. You need an interface list, operating environment, clock and latency requirements, an initial resource estimate, and a plan for configuration. The examples below are hypothetical planning exercises, not measured designs.
Original silent teaching animation with English captions. Use fullscreen for small labels. Conceptual only: not a measured test, pinout, footprint or engineering certification.
Read the complete video transcript
01 MAP INTERFACES Count inputs, outputs, clocks and debug. Keep external voltage domains separate. Pin count alone cannot qualify a bank. Map each interface before comparing families.
02 CHECK BANK CONSTRAINTS Check the exact device and package. Record I/O standards and bank supplies. Keep unresolved bank checks visible. Verify bank and package constraints in exact-device documents.
03 PLAN STARTUP Identify configuration and clock paths. Define required output states at startup. Check the chosen tools and image flow. Plan configuration, clocking and safe startup behavior.
04 ESTIMATE RESOURCES Describe logic, RAM and arithmetic. Constrain representative implementation. A family maximum is not a timing result. Use representative implementation evidence to assess fit.
05 HAND OFF THE SHORTLIST Keep the complete ordering code. Attach document revisions and open checks. Confirm supply for the specific offer. A shortlist is provisional until its mandatory checks close.
Turn the application into checks that can reject a candidate
Write requirements as measurable conditions. “Small industrial controller” does not specify an interface voltage, temperature grade or configuration method. “Twenty-four inputs and sixteen outputs, grouped by external voltage domain, with a defined safe state during configuration” is a useful starting point. Even that statement does not prove that forty user I/O pins are sufficient: reserve configuration, clock and debug connections and check the exact package pinout.
| Decision | Record before selection | Evidence needed to close it |
|---|---|---|
| External interfaces | Signal count, direction, voltage standard, frequency and special pins, grouped by bank | Exact device/package pinout and supported I/O standards; check bank-supply restrictions |
| Logic and storage | Logic estimate, RAM width/depth and port use, arithmetic structure and growth allowance | Architecture tables plus a representative synthesis and implementation report |
| Clocking and timing | Clock sources, required frequencies, clock domains and maximum permitted latency | Clocking resources, timing constraints and timing analysis for the selected grade |
| Power and startup | Available rails, startup behavior, safe output state and configuration source | Electrical and configuration documents for the exact part; board-level verification plan |
| Board and procurement | Package constraints, temperature requirement, build quantity and required date | Complete ordering code, official package information and offer-specific supply confirmation |
Use the product families as investigation paths
The manufacturer’s family pages distinguish feature groups, but a feature mentioned on a portfolio page is not present in every member or package. The following table intentionally avoids family maximum values: those values cannot answer whether your chosen package exposes the needed resources.
| Starting point | Manufacturer portfolio distinction | What still needs checking |
|---|---|---|
| LittleBee / GW1N-related lines | The LittleBee portfolio is presented as flash-based, non-volatile programmable logic, with separately named variants for additional functions. | Exact device resources, startup conditions, configuration options, user I/O by package and grade. Do not assume every variant has integrated RAM beyond its ordinary FPGA memory, a processor or wireless functions. |
| Arora II | The portfolio distinguishes GW2A, integrated-flash GW2AN, integrated-RAM GW2AR and combined GW2ANR lines. | Which memory technology and capacity apply to the exact device, how it connects to the fabric, and whether the required package and tool support exist. |
| Arora V | Separate lines include traditional FPGA, transceiver, integrated-RAM and embedded-processor variants. | Actual protocol/IP availability, device/package transceiver access, clock requirements, tool support and electrical limits. “Arora V” alone does not select a transceiver or processor. |
Sources: LittleBee portfolio and variant headings, Arora II portfolio and variant headings, and Arora V portfolio and variant headings. These are live web portfolios, not fixed-revision electrical specifications. Record the relevant datasheet revision before making an engineering decision.
Example 1: parallel control signals with a defined startup state
Assume a hypothetical design needs forty external control signals, a moderate state machine and a small event buffer. A non-volatile family may be worth investigating because configuration behavior is part of the requirement. Start with the LittleBee portfolio, but do not select a part yet.
- Separate the forty signals into voltage domains and identify inputs that can be active before the FPGA is powered.
- Map each signal to the exact package’s available pins and banks. Count clock, configuration and debug requirements separately.
- Write the event buffer width and depth. Check memory organization and access ports, not only the total bit count.
- Define the safe external state during power-up and configuration. Validate it using the configuration documentation and the board circuitry.
- Run a representative implementation. A logic estimate does not prove routing, clock availability or timing.
The output is a conditional shortlist: “candidate A fits the checked interface allocation; startup behavior and timing remain open.” That is more useful to a reviewer than “this family is ideal for industrial control.”
Example 2: a data path with a serial-link requirement
Assume a second design has an explicitly defined serial protocol and throughput target, plus buffering and arithmetic. Investigate a transceiver-bearing Arora V line rather than assuming ordinary I/O implements the physical interface. This is a direction for research, not a statement that any named device supports the protocol.
Check the protocol’s physical and logical requirements separately: lane count, line rate, reference clock, encoding overhead, transceiver features, IP availability and licensing. Calculate buffering from the allowed back-pressure and latency assumptions. Then verify package routing, power and thermal constraints. If the protocol or required IP is unsupported, reject the candidate even when its logic count is large enough.
Three public product starting points, with explicit limits
The links below are existing public family or product-line guides, not approved exact ordering-code recommendations. They help narrow the investigation while the exact Gowin device evidence is being completed. No private reserve entry is presented as an available product.
- Explore the GW1N product line when non-volatile programmable logic is relevant to your startup requirement. Reject a proposed member if package-specific I/O or required resources do not fit.
- Review the Arora II family when investigating fabric and memory trade-offs. An integrated-memory variant is not interchangeable with a similarly named device without that feature.
- Investigate the GW5AT product line for a design that may need transceiver resources. Confirm the exact protocol, package and tool/IP support before treating it as a candidate.
Keep the complete manufacturer ordering string in your review record, including any slash notation or special suffix exactly as published. Do not create codes by combining family names, package labels and grade fragments from different tables. A source listing establishes identity only within that source’s scope; it does not establish current supply.
Leave with a shortlist someone else can review
For each candidate record: the complete ordering code, relevant document revisions, requirement-to-evidence mapping, assumptions, open checks and the person responsible for validation. Keep engineering suitability and sourcing status in separate columns. A quote cannot close an electrical question, and an implementation report cannot establish delivery availability.
| You have | Next step | Bring these inputs |
|---|---|---|
| A family shortlist with incomplete requirements | Open the engineering tools directory | I/O domains, clock targets, RAM organization and configuration needs |
| A review to share with purchasing or engineering | Find the I/O and power review worksheets | Exact part, board revision, source revisions and unresolved checks |
| A sourcing requirement | Request a Gowin sourcing review | Exact MPN when known, quantity, required date and traceability requirements; supply remains to be confirmed |
| A board implementation to assess | Prepare a PCBA review | BOM, schematic, fabrication/assembly files, stack-up and test expectations |
Frequently asked selection questions
Can I choose only by LUT count?
No. The design can fail on I/O allocation, memory organization, clocking, timing, configuration or tool support before logic capacity becomes the limiting factor. Compare the constraints that matter to your implementation.
Are related Gowin families pin-compatible?
This guide establishes no pin-compatible relationship. Any migration needs a device-specific package/pin, electrical, configuration, toolchain and implementation review, even when two names look similar.
Does a public product page mean the part is in stock?
No. Public documentation and verified identity are separate from a current supplier offer. Confirm quantity, date and traceability for the exact ordering code.
Prepared with AI assistance and source review. No human engineering certification, hardware measurements or availability guarantee is implied. Portfolio sources checked October 23, 2026; exact part qualification remains a project-specific task.