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PS5012-E12

PCIe/NVMe SSD controller with eight NAND channels.

FPGA.io Part Number FIO-A6B76053A831ED99Internal catalogue reference · manufacturer MPN remains unchanged

Technical reference · Base device — ordering suffix not specified · Checked 2026-09-28

PS5012-E12 — technical feature overview
Technical schematicFPGA.io technical schematic for PS5012-E12. Values summarize the documented fields below; consult their source conditions. This is an abstract diagram, not a product photograph, package drawing or pinout. Parameter sources below ↓

DOCUMENTED FACTS

Technical parameters

4 source-linked fields

Values apply to the device and conditions identified in each source. Family maxima, package limits and full ordering-code specifications must not be treated as interchangeable.

ParameterDocumented valueSource & conditions
Host interfacePCIe 3.0 ×4, NVMe 1.3PS5012-E12/E12S controller product brochure ↗Specifications table; E12 package row
NAND channels, up to8PS5012-E12/E12S controller product brochure ↗Specifications table; E12 package row
Flash transfer rate, up to667 MT/sPS5012-E12/E12S controller product brochure ↗Specifications table; E12 package row
Package529-ball TFBGA, 16 × 16 mmPS5012-E12/E12S controller product brochure ↗Specifications table; E12 package row

Official documents

PS5012-E12/E12S controller product brochureSpecifications table; E12 package rowPDF ↗Phison SSD solutionsPCIe 3.0 / PS5012-E12 controller rowWeb ↗

Ordering and board constraints

This reference identifies a base device. Package, speed grade, temperature, qualification and packing suffixes have not been inferred.

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Series & categories

COMPLETE PART IDENTITIES

Ordering numbers for PS5012-E12

0 documented codes

These references belong to this device. Evidence labels distinguish reviewed specifications, public listings and manufacturer coding examples. Counts describe this site’s documented coverage, not stock or all configurations offered by the manufacturer.

Exact ordering code requires confirmation

The cited reference could not be retrieved as usable ordering evidence in this pass. This is an evidence limit, not a claim that no code exists. The existing device identity is retained; no suffix combinations, neighboring chips, boards or systems are substituted.

Ordering identity reference ↗

Ordering identity reference ↗

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