PangoMicro / 紫光同创 / TECHNICAL REFERENCE

PGL12G

Logos FPGA base device.

FPGA.io Part Number FIO-AEE97B7B2F7F2E26Internal catalogue reference · manufacturer MPN remains unchanged

Technical reference · Base device — ordering suffix not specified · Checked 2026-09-28

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PGL12G — technical feature overview — Technical schematicFPGA.io technical schematic for PGL12G. Values summarize the documented fields below; consult their source conditions. This is an abstract diagram, not a product photograph, package drawing or pinout. Parameter sources below ↓

DOCUMENTED FACTS

Technical parameters

3 source-linked fields

Values apply to the device and conditions identified in each source. Family maxima, package limits and full ordering-code specifications must not be treated as interchangeable.

Parameter	Documented value	Source & conditions
Logic elements	12480 LE	Pango Logos series ↗Product selection table; PGL12G column / Logic elements row
Block RAM	540 Kbit	Pango Logos series ↗Product selection table; PGL12G column / Block RAM row
18x18 APM blocks	20 blocks	Pango Logos series ↗Product selection table; PGL12G column / 18x18 APM blocks row

Official documents

Pango Logos seriesProduct selection tableWeb ↗

Ordering and board constraints

This reference identifies a base device. Package, speed grade, temperature, qualification and packing suffixes have not been inferred.

Base-device reference; select and verify the package, speed and temperature suffix separately.
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Series & categories

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COMPLETE PART IDENTITIES

Ordering numbers for PGL12G

0 documented codes

These references belong to this device. Evidence labels distinguish reviewed specifications, public listings and manufacturer coding examples. Counts describe this site’s documented coverage, not stock or all configurations offered by the manufacturer.

Exact ordering code requires confirmation

This bounded review did not verify a literal full ordering code. This does not establish that no code exists. Package, speed and temperature matrices were not expanded.

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