NVIDIA / TECHNICAL REFERENCE

Vera CPU

Vera host CPU with custom Olympus cores.

FPGA.io Part Number FIO-618D73AC7EC09DBDInternal catalogue reference · manufacturer MPN remains unchanged

Technical reference · Base device — ordering suffix not specified · Checked 2026-09-28

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Vera CPU — technical feature overview — Technical schematicFPGA.io technical schematic for Vera CPU. Values summarize the documented fields below; consult their source conditions. This is an abstract diagram, not a product photograph, package drawing or pinout. Parameter sources below ↓

DOCUMENTED FACTS

Technical parameters

5 source-linked fields

Values apply to the device and conditions identified in each source. Family maxima, package limits and full ordering-code specifications must not be treated as interchangeable.

Parameter	Documented value	Source & conditions
CPU cores	88 Olympus	Vera CPU official reference ↗Olympus cores, LPDDR5X memory subsystem and NVLink-C2C
Hardware threads	176	Vera CPU official reference ↗Olympus cores, LPDDR5X memory subsystem and NVLink-C2C
Memory technology	LPDDR5X	Vera CPU official reference ↗Olympus cores, LPDDR5X memory subsystem and NVLink-C2C
Memory bandwidth, up to	1.2 TB/s	Vera CPU official reference ↗Olympus cores, LPDDR5X memory subsystem and NVLink-C2C
NVLink-C2C bandwidth, up to	1.8 TB/s	Vera CPU official reference ↗Olympus cores, LPDDR5X memory subsystem and NVLink-C2C

Official documents

Vera CPU official referenceOlympus cores, LPDDR5X memory subsystem and NVLink-C2CWeb ↗

Ordering and board constraints

This reference identifies a base device. Package, speed grade, temperature, qualification and packing suffixes have not been inferred.

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Series & categories

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COMPLETE PART IDENTITIES

Ordering numbers for Vera CPU

0 documented codes

These references belong to this device. Evidence labels distinguish reviewed specifications, public listings and manufacturer coding examples. Counts describe this site’s documented coverage, not stock or all configurations offered by the manufacturer.

Exact ordering code requires confirmation

Public material establishes the named processor/ASIC identity, but this review did not locate a literal public packaged-chip ordering code. Board, adapter, Superchip, server and system sales codes are not evidence of a bare-chip MPN for this reference.

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