NVIDIA / TECHNICAL REFERENCE

Rubin GPU

Named Rubin GPU package; the surrounding Vera Rubin platform is a separate system.

FPGA.io Part Number FIO-2441189FDF50407CInternal catalogue reference · manufacturer MPN remains unchanged

Technical reference · Base device — ordering suffix not specified · Checked 2026-09-28

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Rubin GPU — technical feature overview — Technical schematicFPGA.io technical schematic for Rubin GPU. Values summarize the documented fields below; consult their source conditions. This is an abstract diagram, not a product photograph, package drawing or pinout. Parameter sources below ↓

DOCUMENTED FACTS

Technical parameters

6 source-linked fields

Values apply to the device and conditions identified in each source. Family maxima, package limits and full ordering-code specifications must not be treated as interchangeable.

Parameter	Documented value	Source & conditions
Compute-die count	2 linked by NV-HBI	Rubin GPU official reference ↗Chip architecture and memory-subsystem sections
Streaming multiprocessors	224	Rubin GPU official reference ↗Chip architecture and memory-subsystem sections
Tensor cores	896	Rubin GPU official reference ↗Chip architecture and memory-subsystem sections
Memory technology	HBM4	Rubin GPU official reference ↗Chip architecture and memory-subsystem sections
Memory capacity, up to	288 GB	Rubin GPU official reference ↗Chip architecture and memory-subsystem sections
Memory bandwidth, up to	22 TB/s	Rubin GPU official reference ↗Chip architecture and memory-subsystem sections

Official documents

Rubin GPU official referenceChip architecture and memory-subsystem sectionsWeb ↗

Ordering and board constraints

This reference identifies a base device. Package, speed grade, temperature, qualification and packing suffixes have not been inferred.

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Do not apply full-chip resource counts to every board or SKU using the chip.
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Series & categories

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COMPLETE PART IDENTITIES

Ordering numbers for Rubin GPU

0 documented codes

These references belong to this device. Evidence labels distinguish reviewed specifications, public listings and manufacturer coding examples. Counts describe this site’s documented coverage, not stock or all configurations offered by the manufacturer.

Exact ordering code requires confirmation

Public material establishes the named processor/ASIC identity, but this review did not locate a literal public packaged-chip ordering code. Board, adapter, Superchip, server and system sales codes are not evidence of a bare-chip MPN for this reference.

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