Montage Technology / 澜起科技 / TECHNICAL REFERENCE
M88RT51632
Sixteen-lane PCIe 5.0 / CXL 2.0 retimer.
FPGA.io Part Number FIO-C9A1372AE009DCF5Internal catalogue reference · manufacturer MPN remains unchanged
Technical reference · Base device — ordering suffix not specified · Checked 2026-09-28
DOCUMENTED FACTS
Technical parameters
Values apply to the device and conditions identified in each source. Family maxima, package limits and full ordering-code specifications must not be treated as interchangeable.
| Parameter | Documented value | Source & conditions |
|---|---|---|
| Link lanes | 16 | M88RT51632 product page ↗Overview and Features |
| SerDes rate | 32 GT/s | M88RT51632 product page ↗Overview and Features |
| Supply rails | 1.8 and 0.9 V | M88RT51632 product page ↗Overview and Features |
| Reference clock | 100 MHz | M88RT51632 product page ↗Overview and Features |
Official documents
M88RT51632 product pageOverview and FeaturesWeb ↗Ordering and board constraints
This reference identifies a base device. Package, speed grade, temperature, qualification and packing suffixes have not been inferred.
- Verify the exact package, grade and ordering suffix before design-in.
- Confirm current availability and lifecycle for the complete code before procurement.
- Review pinout, electrical conditions and the exact document revision before PCB release.
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COMPLETE PART IDENTITIES
Ordering numbers for M88RT51632
These references belong to this device. Evidence labels distinguish reviewed specifications, public listings and manufacturer coding examples. Counts describe this site’s documented coverage, not stock or all configurations offered by the manufacturer.
Exact ordering code requires confirmation
The manufacturer distinguishes M88RT51632TR as a functional product variant with internal AC-coupling capacitors; TR is not established here as a tape-and-reel suffix. It is therefore not added as an ordering-package child of M88RT51632. No complete package ordering row was found.
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