Marvell / TECHNICAL REFERENCE

CN106

OCTEON 10 data processing unit.

FPGA.io Part Number FIO-F148E2DA3CF74F21Internal catalogue reference · manufacturer MPN remains unchanged

Technical reference · Base device — ordering suffix not specified · Checked 2026-09-28

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CN106 — technical feature overview — Technical schematicFPGA.io technical schematic for CN106. Values summarize the documented fields below; consult their source conditions. This is an abstract diagram, not a product photograph, package drawing or pinout. Parameter sources below ↓

DOCUMENTED FACTS

Technical parameters

4 source-linked fields

Values apply to the device and conditions identified in each source. Family maxima, package limits and full ordering-code specifications must not be treated as interchangeable.

Parameter	Documented value	Source & conditions
Maximum Arm Neoverse N2 CPU cores	24 cores	Marvell OCTEON 10 processor announcement ↗OCTEON 10 CN106 paragraph
Integrated switch bandwidth	1 Tb/s	Marvell OCTEON 10 processor announcement ↗OCTEON 10 CN106 paragraph
Inline AI/ML acceleration	Supported	Marvell OCTEON 10 processor announcement ↗OCTEON 10 CN106 paragraph
Vector packet processing hardware acceleration	Supported	Marvell OCTEON 10 processor announcement ↗OCTEON 10 CN106 paragraph

Official documents

Marvell OCTEON 10 processor announcementOCTEON 10 CN106 paragraphWeb ↗

Ordering and board constraints

This reference identifies a base device. Package, speed grade, temperature, qualification and packing suffixes have not been inferred.

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Series & categories

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COMPLETE PART IDENTITIES

Ordering numbers for CN106

0 documented codes

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The cited reference could not be retrieved as usable ordering evidence in this pass. This is an evidence limit, not a claim that no code exists. The existing device identity is retained; no suffix combinations, neighboring chips, boards or systems are substituted.

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