An IC package name carries four stacked layers: a generic family abbreviation, a JEDEC outline that fixes the exact dimensions, a manufacturer’s package designator glued into the part number, and a packing or quality suffix. IC package naming conventions trip up engineers because the same package wears a different code at every vendor. This guide decodes each layer so you order the right footprint, not just the right silicon.
[IMAGE 1: an annotated part number SN74LVC1G08DBVR with each segment labeled (prefix, function, package code, packing) | alt: “IC package naming conventions decoded: SN74LVC1G08DBVR part number broken into prefix, function, package code DBV, and reel suffix R”]
Key takeaways
- A package name has four layers: generic family (SOIC), JEDEC outline (MS-012), vendor designator (TI “D”), and packing suffix (R for reel).
- The generic abbreviation is a grammar you can read: T = thin, S = shrink, Q = quad, F/N = flat no-lead, so TQFP = Thin Quad Flat Pack.
- “Same package name” does not guarantee footprint compatibility — same JEDEC outline does. SOIC narrow is MS-012; SOIC wide is MS-013.
- The package designator differs by manufacturer: TSSOP is “PW” at TI, “ST” at Microchip, “RU” at Analog Devices. The datasheet’s ordering table is the only authority.
- Suffixes carry ordering-critical data: /NOPB or Z means Pb-free, R means tape-and-reel, -Q1 means AEC-Q100 automotive.
The anatomy of a package name
An IC package name is built from four layers: a generic family abbreviation (like SOIC or QFN) that names the shape, a JEDEC registered outline (like MS-012) that fixes the millimeter dimensions, a manufacturer package designator (a letter code inside the part number), and a packing or quality suffix (reel, Pb-free, automotive). Read all four and you know exactly what will land on your board.
Most confusion comes from treating the generic name as the whole story. “SOIC-8” tells you the family and pin count, but two SOIC-8 parts can differ in body width and lead form unless they share a JEDEC outline. The vendor designator, meanwhile, is a private shorthand — decoding it wrong is how the right chip arrives in a footprint your stencil can’t place.
[IMAGE 2: a four-layer stack diagram — generic name, JEDEC outline, vendor designator, packing suffix — with SOIC-8 example filling each layer | alt: “Four layers of an IC package name: generic family, JEDEC outline MS-012, vendor designator, and packing suffix”]
Decoding the generic family abbreviation
The generic abbreviation is not arbitrary. Each letter is a modifier, and they stack in a predictable order. Once you know the pieces, an unfamiliar acronym decodes on sight.
| Element | Meaning | Appears in |
| SO / SOP / SOIC | Small Outline (gull-wing, two sides) | SOIC, SOP |
| S (shrink) | Shrink — finer lead pitch | SSOP, QSOP |
| T (thin) | Thin — reduced height | TSSOP, TQFP, TSOP |
| V | Very thin or very small | VSSOP, VQFN, VSOP |
| U | Ultra-thin | UQFN, UDFN |
| Q | Quad — leads on four sides | QFP, QFN |
| F + N | Flat, No-lead (pads, no leads) | QFN, DFN |
| D | Dual — two sides / two rows | DIP, DFN, DPAK |
| L | Low-profile, or Leadless | LQFP, LCC |
| P | Plastic, or Pin (grid) | PDIP, PLCC, PGA |
| C | Ceramic, or Chip (scale) | CDIP, CQFP, CSP |
| BGA / LGA / PGA | Ball / Land / Pin grid array | BGA, LGA, PGA |
Worked reads: TQFP is Thin Quad Flat Pack. VQFN is Very-thin Quad Flat No-lead. MSOP is a mini/micro Small-Outline Package. WLCSP is a Wafer-Level Chip-Scale Package. The grammar also predicts assembly difficulty — anything with “shrink,” “thin,” or “no-lead” pushes you toward finer pitch and reflow.
Pin count attaches to the family name directly. The rule is family plus pin count: an 8-pin small outline is SOIC-8 or SO-8, a 100-pin low-profile quad flat pack is LQFP-100. Per Wikipedia’s SOIC entry, the convention is simply “SOIC” or “SO” followed by the pin number. One exception matters: for a BGA, pin count alone is ambiguous — you also need the array layout and ball pitch, because a 256-ball part can be many physical sizes.
JEDEC JEP95 outlines: what “same package” really means
Footprint compatibility is defined by the JEDEC outline, not the marketing name. JEP95 is JEDEC’s registry of registered and standard package outlines — roughly 3,000 pages and over 500 registrations maintained by the JC-11 committee, per JEDEC. Each outline fixes the body size, lead span, pitch, and tolerances a footprint must match.
The prefix tells you the category. Per JEDEC’s JEP95 documentation, TO covers transistor outlines (TO-3, and SOT-23 is registered as TO-236), DO covers diodes (DO-41), MO covers registered microelectronic outlines, and MS covers standard microelectronic outlines.
| Family | JEDEC outline | Key dimension |
| PDIP (0.3″ row) | MS-001 | 2.54 mm pitch |
| SOIC narrow | MS-012 | 1.27 mm pitch, 3.9 mm body |
| SOIC wide | MS-013 | 1.27 mm pitch, 7.5 mm body |
| TSSOP | MO-153 | 0.65 mm pitch, ≤1.2 mm high |
| TSSOP, exposed pad, fine pitch | MO-194 | 0.4 mm pitch |
| QFP | MO-086 | pins four sides |
| TQFP / LQFP | MS-026 | 1.4 mm high (LQFP) |
| QFN | MO-220 | no-lead, four sides |
| PLCC | MO-047 | J-lead, 1.27 mm pitch |
| SOT-23 | TO-236 | small-signal transistor |
The practical takeaway: when a datasheet says “compliant to JEDEC MO-153,” any MO-153 land pattern will fit it, regardless of which vendor made the part. Analog Devices’ own TSSOP drawings, for example, state compliance to MO-153, which is how you confirm cross-vendor footprint interchangeability.
Manufacturer package designators: the vendor-suffix problem
Here is where naming gets messy. Each manufacturer assigns its own letter code for a package and drops it into the orderable part number. The codes do not agree across vendors, so the same physical TSSOP is “PW,” “ST,” or “RU” depending on who built it.
| Package | Texas Instruments | Microchip | Analog Devices |
| PDIP | N | P | N |
| SOIC narrow | D | SN | R / RN |
| SOIC wide | DW | SO | RW |
| SSOP | DB | SS | RQ |
| TSSOP | PW | ST | RU |
| MSOP / VSSOP | DGK | MS | RM |
| QFN / LFCSP | RGE, RHB | ML | CP |
| DFN | — | MF | — |
| TQFP / LQFP | PT | PT | — |
| SOT-23 (5-lead) | DBV | OT | — |
TI codes such as D (SOIC), DW (wide SOIC), and PW (TSSOP) come from TI device datasheets; Microchip’s P, SN, SO, SS, and ST come from Microchip Packaging Specification DS00049; Analog Devices’ RU (TSSOP) is confirmed by its MO-153 outline drawing. Treat this table as a starting map. The authoritative source is always the specific datasheet’s ordering-information and package-marking section, because vendors add variants and exceptions.
Distributors add one more translation layer. On DigiKey, the “Supplier Device Package” field shows the manufacturer’s own name, while “Package / Case” normalizes to an industry-standard descriptor, per DigiKey’s package reference. When you cross-shop two vendors, compare the Package/Case field, not the supplier name.
The full part number, decoded
Put the layers together and any orderable becomes readable. The general anatomy is prefix + base function + package designator + temperature/grade + packing/quality suffix.
Worked example one: SN74LVC1G08DBVR. “SN” is TI’s standard prefix, “74LVC” is the logic family, “1G08” is a single 2-input AND gate, “DBV” is the SOT-23-5 package, and the trailing “R” is tape-and-reel, per TI logic documentation and PCBSync’s TI decode. Swap DBV for DGK or RGE and you have changed the footprint and stencil without changing the function.
Worked example two: LM358MX/NOPB. “LM358” is the dual op-amp, “M” is the 8-lead SOIC, “X” indicates tape-and-reel on this legacy National-lineage part, and “/NOPB” marks it Pb-free (no lead), per TI’s part-number guidance. The same die in tube shipping drops the X; the leaded version drops the /NOPB.
Packing, Pb-free, and qualification suffixes
The tail of a part number is not decoration. It controls how the part ships and whether it belongs on your BOM.
| Suffix | Meaning | Vendor usage |
| R | Tape-and-reel | TI (e.g., D→DR), Microchip reel codes |
| X | Tape-and-reel (legacy) | TI/National (e.g., LM358MX) |
| T | Small/tiny reel | TI |
| /NOPB | Pb-free (no lead) | TI/National |
| G, G4 | Green / Pb-free variant | TI |
| Z | RoHS / Pb-free | Analog Devices (e.g., …CPZ) |
| EP | Enhanced Product, −55 to 125 °C | TI high-reliability |
| -Q1 | AEC-Q100 automotive-qualified | TI |
Two of these are ordering traps. A part without /NOPB, G, or Z may be the leaded version and non-RoHS, per TI and DigiKey suffix references. And a part without the -Q1 suffix is not AEC-Q100 qualified and does not belong on an automotive BOM, per PCBSync’s TI sourcing guidance, no matter how well the specs read.
Master decode table
| Package family | Generic name | JEDEC outline | TI | Microchip | ADI |
| Plastic DIP | PDIP-N | MS-001 | N | P | N |
| Small outline (narrow) | SOIC-N | MS-012 | D | SN | R |
| Small outline (wide) | SOIC-N | MS-013 | DW | SO | RW |
| Shrink small outline | SSOP | MO-150 | DB | SS | RQ |
| Thin shrink small outline | TSSOP | MO-153 | PW | ST | RU |
| Micro small outline | MSOP / VSSOP | MO-187 | DGK | MS | RM |
| Quad flat no-lead | QFN / LFCSP | MO-220 | RGE | ML | CP |
| Low-profile quad flat pack | LQFP | MS-026 | PT | PT | — |
| Small-signal transistor | SOT-23 | TO-236 | DBV | OT | — |
How to decode any package name
Run these steps on any unfamiliar code.
- Split the part number. Separate the base function from the trailing letters. The package designator sits between the function and the packing suffix.
- Open the datasheet’s ordering table. Match the exact orderable string; the ordering and package-marking sections define what each letter means for that vendor.
- Map the generic family to a JEDEC outline. Confirm the outline (MS-012, MO-153, and so on) so you know which land pattern fits.
- Read the packing and quality suffix. Confirm reel versus tube, Pb-free status, and automotive qualification before you order.
- Cross-check the distributor field. Compare the Package/Case descriptor across suppliers, not the supplier’s own package name.
[IMAGE 3: decode-path flowchart from part number through datasheet ordering table, JEDEC outline, packing suffix, to a verified footprint | alt: “Flowchart to decode an IC package name: split part number, datasheet ordering table, JEDEC outline, packing suffix, verify footprint”]
Naming mistakes that cause wrong orders
- Ordering the wrong package suffix. The same silicon in DBV, DGK, and RGE is three different footprints. The cheapest line item may be a package your line cannot place.
- Treating the generic name as footprint-compatible. Two “SOIC-8” parts can differ in body width. Match the JEDEC outline, not the family name.
- Confusing imperial and metric size codes. This bites passives more than ICs, but shrink-package body dimensions are quoted in millimeters even when the family name implies otherwise.
- Missing the Pb-free tail. Ordering without /NOPB, G, or Z can deliver a leaded, non-RoHS part.
- Ignoring lifecycle and qualification. An NRND part forces a redesign, and a part without -Q1 fails automotive qualification.
- Copying the datasheet drawing instead of the IPC-7351 land pattern. Vendor package drawings vary within an outline; use IPC-7351 and verify against the datasheet.
FAQ
What do the letters and numbers in an IC package name mean?
An IC package name has four layers: a generic family abbreviation (SOIC, QFN), a JEDEC outline that fixes the dimensions (MS-012), a manufacturer package designator inside the part number (TI’s “D”), and a packing or quality suffix (R for reel, /NOPB for Pb-free). Together they define the exact part.
What does the suffix on an IC part number mean?
The suffix usually encodes the package and how the part ships. A letter or two identifies the package (TI’s PW is TSSOP), and trailing characters give packing and status: R or X for tape-and-reel, /NOPB or Z for Pb-free, -Q1 for automotive. Always confirm against the datasheet ordering table.
What is a JEDEC package outline?
A JEDEC outline is a registered mechanical drawing in JEP95 that fixes a package’s body size, lead pitch, span, and tolerances. Examples include MS-012 for narrow SOIC and MO-153 for TSSOP. Two parts sharing the same outline are footprint-compatible regardless of manufacturer, which is the real test of interchangeability.
What does SOIC-8 mean?
SOIC-8 is a Small Outline Integrated Circuit package with 8 gull-wing leads, four per side. The number is the pin count, and the name follows the family-plus-pins convention. Body width still varies: narrow SOIC follows JEDEC MS-012, wide-body SOIC follows MS-013, so confirm the outline before laying out the footprint.
What is the difference between a package type and a footprint?
The package type is the physical part (SOIC-8, QFN-32). The footprint is the copper land pattern you draw on the PCB to solder it. One package maps to a standardized land pattern defined by IPC-7351, but manufacturers vary slightly within a JEDEC outline, so verify pad dimensions against the specific datasheet.
What does /NOPB mean on a part number?
/NOPB means “no lead” in the elemental sense — the part is Pb-free and RoHS-compliant, a suffix used on Texas Instruments and former National Semiconductor devices. The same part without /NOPB may be the older leaded version. Analog Devices uses a trailing “Z” for the same Pb-free status.
The bottom line
Decode a package name from the outside in. Split the part number, then read the layers: family abbreviation for the shape, JEDEC outline for the dimensions, vendor designator for who made it, and the tail for packing and status. When you need a second source, match on the JEDEC outline — MS-012, MO-153, MO-220 — because that, not the marketing name, is what guarantees the footprint fits. And before any order goes out, confirm the Pb-free and qualification suffix against the datasheet’s ordering table, so the right silicon shows up in the package your line can actually build.
Internal links: electronic component packages (types overview) · hermetic packages (ceramic/metal-can) · IPC-7351 land patterns · moisture sensitivity level (MSL) · AEC-Q100 automotive qualification.
External primary sources: JEDEC JEP95 registered outlines (jedec.org); TI packaging terminology (ti.com); Microchip Packaging Specification DS00049 (microchip.com); Analog Devices RU/TSSOP outline, MO-153 (analog.com); TI device datasheet package/ordering data (ti.com).
