An electronic component package is the housing that protects a die or element, connects it to the board, and sets the footprint you route to. The package you pick decides your pin density, your assembly line, your thermal headroom, and how a part is inspected and reworked. This guide maps every major family, gives verified pitches and dimensions, and adds the two numbers the package name hides — thermal resistance and moisture sensitivity — so you can choose without guessing.
[IMAGE 1: side-by-side silhouettes of DIP, SOIC, TSSOP, QFN, and BGA at the same scale | alt: “Electronic component packages compared: DIP, SOIC, TSSOP, QFN, and BGA outlines to scale”]
Key takeaways
- Every package is classified two ways at once: mounting method (through-hole or surface-mount) and terminal style (leaded, no-lead, or ball/land array).
- The size code on a chip resistor is imperial by default: 0402 means 1.0 × 0.5 mm, not 0.4 × 0.2 mm — that metric size is 01005.
- Lead pitch drives solderability. 1.27 mm (SOIC) is hand-friendly; below 0.5 mm (fine-pitch QFP, QFN, BGA) is a reflow-and-X-ray job.
- Two parts with the same silicon can differ 2× in thermal resistance purely by package — the copper the tab or pad touches is the real heatsink.
- Fine-pitch plastic parts are moisture-sensitive. An MSL 3 reel has a 168-hour floor life once the dry bag is opened, per IPC/JEDEC J-STD-020.
What an electronic component package actually is
An electronic component package is the standardized mechanical body that encloses a semiconductor die or passive element, provides the terminals that carry signals and power to the PCB, conducts heat away from the die, and defines a repeatable footprint for automated assembly. Packages are classified by how they mount, how their terminals are shaped, and how many terminals they carry.
That four-part job — protect, connect, cool, standardize — is why the same circuit can ship in a dozen package options. A microcontroller offered in DIP, TSSOP, QFN, and BGA is one design in four bodies, each trading board area for assembly difficulty.
How electronic component packages are classified
Two axes describe any package. Get both and you can name almost anything on a board.
By mounting method: through-hole vs surface-mount
Through-hole technology (THT) pushes leads through drilled, plated holes and solders them on the far side. It gives a strong mechanical joint and tolerates hand assembly, which is why connectors, large electrolytics, and power devices under mechanical stress still use it.
Surface-mount technology (SMT) places terminals directly on pads on the board surface. Surface-mount devices (SMDs) are smaller, support fully automated pick-and-place, and shorten lead lengths, which lowers parasitic inductance and helps high-frequency performance. SMT dominates modern production; through-hole survives where mechanical strength or power handling wins.
By terminal style
Within SMT, terminals take three broad shapes. Leaded packages expose metal leads — gull-wing (SOIC, QFP) for visible, inspectable joints, or J-lead (PLCC) folded under the body. No-lead packages (QFN, DFN) replace leads with pads flush to the package edge, saving area but hiding the joint. Array packages (BGA, LGA) put connections on the underside as a grid of solder balls or flat lands, which is the only practical way to break out hundreds or thousands of I/O.
Through-hole packages
Through-hole packages share a 2.54 mm (100 mil) lead grid, the spacing that matches perfboard and older automated insertion.
The DIP (Dual In-line Package) has two parallel lead rows on a 2.54 mm pitch, in 300 mil (narrow) or 600 mil (wide) body widths. It is the classic logic and microcontroller body for prototyping and sockets. TO-92 is the small three-lead plastic transistor case. For power, TO-220 and the larger TO-247 carry a metal tab for bolting to a heatsink; TO-220 covers most commercial designs up to roughly 50 W of dissipation, per the Infineon/International Rectifier IRF640N datasheet. Axial (resistors, diodes) and radial (electrolytics, film capacitors) round out the through-hole discretes.
Use through-hole when a joint must survive vibration or repeated connector mating, or when you are hand-building prototypes.
Surface-mount passives and the size-code system
Chip resistors, capacitors, and inductors use a numeric size code — and the code is a common trap. The standard EIA code is imperial: the digits are body length and width in hundredths of an inch. So 0603 means 0.060 × 0.030 in ≈ 1.6 × 0.8 mm. The IEC metric name for that same part is 1608. The collision to watch: imperial 0402 (1.0 × 0.5 mm) is a completely different part from metric 0402 (0.4 × 0.2 mm), which is imperial 01005. Read the datasheet’s unit before you order.
| Imperial | Metric | Body (mm) | Typical power (thick-film, 70 °C) | Notes |
| 01005 | 0402 | 0.4 × 0.2 | ~31 mW | Wearables/mobile; advanced assembly only |
| 0201 | 0603 | 0.6 × 0.3 | ~50 mW | High-density boards |
| 0402 | 1005 | 1.0 × 0.5 | ~63 mW | Mainstream small |
| 0603 | 1608 | 1.6 × 0.8 | ~100 mW | The general-purpose default |
| 0805 | 2012 | 2.0 × 1.25 | ~125 mW | Easiest reliable hand-solder |
| 1206 | 3216 | 3.2 × 1.6 | 250 mW | Higher power / hand assembly |
| 1210 | 3225 | 3.2 × 2.5 | ~500 mW | Power / high-value MLCC |
| 2010 | 5025 | 5.0 × 2.5 | ~500–750 mW | Current sense, power |
| 2512 | 6332 | 6.3 × 3.2 | ~1 W | High-power sense resistors |
Power scales with body size because larger parts have more ceramic mass and termination area to sink heat into the copper. Ratings are quoted at 70 °C and derate above it: a 1206 rated 250 mW at 70 °C is only good for about 125 mW at 100 °C, per JLCPCB and BestPCB chip-resistor data. For MLCCs there is a second trap — DC bias. A small ceramic capacitor loses effective capacitance as applied voltage rises, so a Class-II 0402 near its voltage rating can read a fraction of its marked value in circuit.
Leaded IC packages: small-outline and quad-flat
Leaded IC bodies span a wide pitch range, and pitch is the single number that predicts how hard a part is to assemble and inspect.
| Package | Pitch | Typical pins | Notes |
| SOIC / SOP | 1.27 mm (50 mil) | 8–28 | Narrow 3.9 mm or wide 7.5 mm body; hand-solderable; JEDEC MS-012 / MS-013 |
| SSOP | 0.635–0.65 mm | 8–56 | Shrunk SOIC; reflow preferred |
| TSSOP | 0.65 mm (0.5 mm exists) | 8–80 | Thin ≤1.2 mm body; JEDEC MO-153 |
| QSOP | 0.635 mm | 16–24 | Fine-pitch small outline |
| SOT-23 / SOT-223 | ~0.95 / 2.3 mm | 3–8 | Transistors, regulators, small logic |
| QFP / LQFP / TQFP | 0.4–0.8 mm | 32–256 | Gull-wing on four sides; LQFP body height 1.4 mm; JEDEC MS-026 |
SOIC (Small Outline IC) is the JEDEC name; SOP is the JEITA/IEC name for the same 1.27 mm gull-wing family, and the terms are used interchangeably. Its 1.27 mm pitch tolerates automated placement and stays manageable under a fine-tip iron. SSOP and TSSOP halve the pitch to ~0.65 mm for higher density in the same or smaller footprint, at the cost of tighter fabrication and assembly. QFP and its low-profile variant LQFP bring leads out on all four sides for 32 to 256 pins.
A practical solder line: most engineers can hand-solder down to 0.65 mm (TSSOP, SSOP) with flux and a fine tip. At 0.5 mm LQFP and below, reflow with a stencil is strongly preferred.
Every one of these bodies has a JEDEC registered mechanical outline under JEP95 — SOIC narrow is MS-012, SOIC wide is MS-013, TSSOP is MO-153. Design your land pattern to the outline and to IPC-7351, then confirm against the specific datasheet, because manufacturers vary within an outline.
[IMAGE 2: pitch ruler showing 2.54 mm, 1.27 mm, 0.65 mm, 0.5 mm, and 0.4 mm lead spacings with a “hand-solder limit” marker at 0.65 mm | alt: “Lead pitch comparison from 2.54 mm through-hole to 0.4 mm fine-pitch with hand-solder limit”]
No-lead and array packages: QFN, BGA, and chip-scale
When pin count climbs or board area shrinks, leads disappear.
QFN (Quad Flat No-lead) and its two-sided sibling DFN put pads flush to the package edge plus an exposed thermal pad on the belly. Pitch runs 0.4–0.65 mm, pins reach 70-plus, and the footprint is very small. The catch: joints sit under the body, so the exposed pad needs its own paste opening and thermal vias, and inspection wants X-ray. QFN and DFN are not pin-compatible — the pad geometries differ — though many ICs offer both, so check the datasheet’s package options.
BGA (Ball Grid Array) replaces leads with a grid of solder balls underneath. Pitch spans 1.27 mm down to 0.3–0.35 mm on 2026 phone and wearable parts, and I/O reaches into the thousands. Standard pitches are 1.0 and 0.8 mm; 0.8 mm is common on FPGAs and network chips, per PCBonline assembly data. Ball diameters run roughly 0.55–0.75 mm on standard BGAs and about half that on chip-scale parts.
BGAs have one property that makes them more forgiving than they look: self-alignment. As the balls melt, surface tension pulls the package toward the centroid of its pads, so a part placed up to ~50% off-pad usually snaps into position during reflow, per PCBSync’s assembly guidance. The trade you accept is that you cannot see or touch the joints once formed — you inspect by X-ray, target a voiding rate under 5%, and if you reuse a part you reball it against an IPC-7711 stencil with balls matched to the original.
CSP (Chip-Scale Package) and WLCSP (Wafer-Level CSP) shrink the body to roughly die size. Analog Devices’ AN-617 documents WLCSP arrays at 0.5 mm pitch with balls as small as 150 µm on 110 µm pads. LGA (Land Grid Array) uses flat lands instead of balls for a lower profile.
Master comparison table
| Package | Mount | Pitch | Typical pins | Solderability | Inspection | Relative footprint |
| DIP | THT | 2.54 mm | 4–64 | Easy (hand) | Visual | Large |
| TO-220 / TO-247 | THT | 2.54 mm | 3–5 | Easy (hand/wave) | Visual | Large + heatsink |
| Chip (0402–1206) | SMT | n/a | 2 | 0805 easy; 0402 reflow | Visual | Tiny |
| SOIC / SOP | SMT | 1.27 mm | 8–28 | Hand-solderable | Visual/AOI | Medium |
| SSOP / TSSOP | SMT | 0.65 mm | 8–80 | Reflow preferred | Visual/AOI | Small |
| DPAK / D2PAK | SMT | ~2.28 mm | 3–5 | Reflow/hand | Visual | Medium + copper |
| QFP / LQFP | SMT | 0.4–0.8 mm | 32–256 | Reflow (0.5 mm+) | Visual/AOI | Medium |
| QFN / DFN | SMT | 0.4–0.65 mm | up to ~76 | Reflow only | X-ray | Very small |
| BGA | SMT | 0.3–1.27 mm | 8–1000+ | Reflow only | X-ray | Smallest per pin |
| WLCSP | SMT | 0.35–0.5 mm | up to ~200 | Reflow only | X-ray | ≈ die size |
How to choose an electronic component package
Run the decision in this order and most choices fall out on their own.
- Pin count first. A handful of pins fits SOT, SOIC, or a small QFN. Hundreds force QFP, QFN, or BGA. Above ~256 I/O, BGA is effectively mandatory.
- Match your assembly capability. Hand-building or basic hot air? Stay at 0.65 mm pitch and 0805 passives. No X-ray or fine-pitch line? Avoid BGA and 0.4 mm QFN.
- Check the thermal path. For power parts, the package’s copper interface — tab or exposed pad — is the heatsink. Size the plane to the datasheet, not the schematic.
- Respect the height budget. Thin products need TSSOP, LQFP, QFN, or WLCSP; a wide-body SOIC or DIP may not fit under a shield.
- Confirm lifecycle and a second source. Prefer a body offered by more than one vendor, and check that the package is not near end-of-life before you commit a land pattern.
[IMAGE 3: decision-path flowchart from pin count through assembly, thermal, height, and second-source to a package family | alt: “Electronic component package selection flowchart: pin count, assembly, thermal, height, second source”]
The two specs the package name hides
Thermal resistance: same die, different numbers
Package choice changes thermal performance even when the silicon is identical. Take the IRF640N MOSFET: the same die ships as a TO-220 (IRF640N), a surface-mount D2PAK (IRF640NS), and a TO-262/I-PAK (IRF640NL), rated 150 W dissipation at a 25 °C case and a 175 °C maximum junction, per the International Rectifier datasheet.
Now the package physics. Per ST application note AN1703, a D2PAK in free air has a junction-to-ambient resistance of 62.5 °C/W — the same as a TO-220 — but soldered to its recommended 120 mm² drain-pad copper, junction-to-PCB resistance falls to 42 °C/W. The smaller DPAK starts at 100 °C/W in free air and reaches 62 °C/W on its recommended 45 mm² footprint. The DPAK outline is about 65 mm² versus roughly 150 mm² for D2PAK, per Nexperia. The lesson: a surface-mount power part is only as cool as the copper you give it, and two footprints of the same die can differ nearly 2× in thermal resistance.
Worked check: to hold a 100 °C junction rise while dissipating 2 W, you need a total junction-to-ambient path under 50 °C/W. A bare D2PAK in still air (62.5 °C/W) misses it; the same part on adequate copper (42 °C/W) clears it with margin.
Moisture sensitivity level (MSL)
Plastic packages absorb moisture, and at reflow that moisture flashes to steam and can crack the body — the “popcorn” failure. Parts are graded by Moisture Sensitivity Level under IPC/JEDEC J-STD-020, with handling defined in J-STD-033. The floor-life clock starts when you open the dry bag.
| MSL | Floor life (≤30 °C / 60% RH) | Handling |
| 1 | Unlimited (at ≤30 °C / 85% RH) | No dry pack |
| 2 | 1 year | Dry pack |
| 2a | 4 weeks | Dry pack |
| 3 | 168 hours (7 days) | Most common for plastic ICs |
| 4 | 72 hours | Tight tracking |
| 5 | 48 hours | Dry-cabinet storage |
| 5a | 24 hours | Use promptly |
| 6 | Time-on-label; bake before reflow | Most sensitive |
The scale is non-linear: floor life drops 50× between MSL 2 (one year) and MSL 3 (168 hours), per Cosolvic’s J-STD-020 summary. Exceed the floor life and you bake — typically 125 °C for 24 hours on thin bodies, up to 192 hours on bodies ≥4.5 mm thick, per J-STD-033. Thin packages carry worse ratings because, by Fick’s law, moisture uptake scales with the square of package thickness. Fine-pitch BGAs, QFNs, and large QFPs are the usual MSL 3 offenders — miss the reel’s floor life on an MSL 3 BGA and it can crack internally at a 260 °C peak, surfacing months later as intermittent joints.
Design mistakes that cause field returns
- Drawing pads from body size. The land pattern includes solder fillet and tolerance. Use IPC-7351 or the datasheet, never the component outline alone.
- Confusing imperial and metric codes. Ordering metric 0402 when you meant imperial 0402 gets you a part a quarter of the size you expected.
- Ignoring MLCC DC bias. Swapping an 0805 decoupling cap for an 0402 of the same marked value can leave a fraction of the capacitance in circuit.
- Tombstoning passives. If one pad ties to a large copper plane and the other to a thin trace, the plane side heats slower, the trace side melts first, and surface tension stands the part on end. Balance the thermal reliefs.
- No A1 marking or wrong QFN venting. BGAs need a clear A1 corner for orientation; QFN thermal pads need paste windowpaning and vias, or trapped flux voids the joint.
- Skipping MSL tracking. Untracked floor life on moisture-sensitive reels is a latent field failure.
[IMAGE 4: microscope photo comparison of a good chip-resistor joint versus a tombstoned part | alt: “Correct SMD solder joint versus a tombstoned chip resistor standing on end”]
FAQ
What are the main types of electronic component packages?
They fall into two mounting families. Through-hole packages (DIP, TO-220, axial, radial) push leads through the board. Surface-mount packages mount on pads and include chip passives (0402, 0603), small-outline and quad-flat leaded ICs (SOIC, TSSOP, QFP), no-lead parts (QFN, DFN), and array packages (BGA, CSP) for the highest pin counts.
What is the difference between surface-mount and through-hole?
Through-hole leads pass through drilled holes and solder on the far side, giving a strong joint suited to connectors and power parts. Surface-mount devices sit on surface pads, are smaller, and support full automation. SMT dominates production; through-hole is used where mechanical strength or power handling matters more than density.
What do the numbers on SMD packages like 0402 or 0603 mean?
They are body dimensions in the imperial (inch) system, in hundredths of an inch. 0603 means 0.060 × 0.030 in, about 1.6 × 0.8 mm. The same part in metric is 1608. Watch the collision: imperial 0402 (1.0 × 0.5 mm) is not metric 0402 (0.4 × 0.2 mm), which is imperial 01005.
Can you hand-solder a QFN or BGA?
BGAs cannot be hand-soldered because their joints are hidden under the package and need reflow plus X-ray inspection. QFNs are reflow parts too, since the exposed thermal pad won’t solder reliably with an iron. For hand assembly, stay with gull-wing leaded packages down to about 0.65 mm pitch.
What is the difference between QFN and DFN?
Both are no-lead surface-mount packages with pads flush to the edge. QFN has pads on all four sides; DFN has pads on two sides only. They are not pin-compatible because the footprints differ, but many ICs are offered in both, so check the manufacturer’s package options.
What is moisture sensitivity level (MSL)?
MSL grades how much moisture a plastic package can absorb before reflow risks cracking it, per IPC/JEDEC J-STD-020. MSL 1 has unlimited floor life; MSL 3, the common rating for plastic ICs, allows 168 hours out of the dry bag before you must reflow or bake the parts.
The bottom line
Choose the package by working the decision path, not by copying the last design. If you are hand-building or running a basic SMT line, cap yourself at 0.65 mm pitch and 0805 passives and you will keep yield high. If pin count pushes you past a few hundred I/O, commit to BGA and budget for X-ray and reballing before you route. For any power part, size the copper to the datasheet’s thermal number first — the package is just the interface to the heatsink you design. And whatever you pick, pull the land pattern from IPC-7351 and the datasheet, and track the MSL on the reel. Do those four things and the package stops being a risk and becomes a lever.
Internal links: SMT vs through-hole assembly · IPC-7351 land patterns · BGA routing and fanout · MOSFET selection guide · decoupling capacitor selection.
External primary sources: ST AN1703 thermal guidance (st.com); Analog Devices AN-617 WLCSP (analog.com); TI SPRABY1 MSL and reflow (ti.com); Microchip moisture-sensitivity note (microchip.com); Broadcom J-STD-020 MSL note (broadcom.com).
