The same physical package can appear under five different names, and this IC package cross-reference maps them so you can tell when MLF, LFCSP, and VQFN
A datasheet’s package drawing labels every measurement with a letter, not a name, and getting IC package body size wrong by confusing body with lead span
The package sets three things the silicon cannot: how much heat you can pull out, how much parasitic inductance sits in series with your switching
Memory arrives in two distinct tiers, and confusing them is the most common mistake in a sourcing spreadsheet. TSOP and FBGA are chip-level packages that hold one
Four LED package types cover almost every board-level lighting decision: SMD, COB, CSP, and PLCC. SMD gives you discrete, individually driven dies. COB fuses dozens of
A leadless package connects to the board through metallized pads or lands on the bottom of its body, not through leads that bend out the sides.
A JEDEC package outline is a registered mechanical drawing that fixes a package’s exact dimensions and tolerances, and it is the real definition of whether two
Inductors use two separate naming worlds, and mixing them up gets the wrong part on your board. Small chip inductors follow the EIA case codes
An IC package name carries four stacked layers: a generic family abbreviation, a JEDEC outline that fixes the exact dimensions, a manufacturer’s package designator glued
A hermetic package seals a die inside an airtight cavity made of metal, ceramic, or glass, blocking the moisture and contaminants that kill high-reliability electronics. Plastic