Post: VSSOP-10 Package: Dimensions and Land Pattern

Components Packages

VSSOP-10 Package: Dimensions and Land Pattern

VSSOP-10 is Texas Instruments’ 10-lead package, code DGS, registered under JEDEC MO-187 variation BA — a roughly 3.0 × 3.0 mm body at 0.5 mm pitch, 1.1 mm max height. Unlike the 8-lead VSSOP naming split covered elsewhere on this site, TI’s 10-lead VSSOP doesn’t have a second, conflicting package hiding behind the same name — DGS is the only game in town, and its numbers are verified directly from TI’s own package drawing below.

Key takeaways

TI’s DGS0010A package drawing explicitly states “Reference JEDEC registration MO-187, variation BA” — the same generic MSOP-10 outline used industry-wide.
Body/lead-tip span: 4.75–5.05 mm; max height 1.1 mm; lead pitch 0.5 mm; lead width 0.17–0.27 mm — all sourced from TI’s own mechanical drawing.
TI’s example land pattern uses 1.45 × 0.3 mm pads on 0.5 mm centers with a 4.4 mm symmetric span.
At least one distributor-facing aggregator page describes VSSOP-10/DGS as “leadless” with an “exposed thermal pad.” Both false. TI’s own thermal data lists junction-to-case-bottom resistance as not applicable, meaning no exposed pad, and the package drawing shows conventional gull-wing leads.
Real, currently active TI parts in this package span ADCs (ADS1015, ADS1013, ADS1115), a DAC (DAC8562), an op-amp (TLV2373), and a timer (TPL5000) — a genuinely broad application range, not a niche outline.

Package Identification: DGS, JEDEC MO-187 Variation BA

TI’s own package drawing for the 10-lead VSSOP (document 4221984/A, drawing DGS0010A) states directly: “Reference JEDEC registration MO-187, variation BA.” This is the same registration confirmed independently for generic MSOP-10 across other manufacturers’ datasheets — meaning VSSOP-10 (TI’s name) and MSOP-10 (the generic industry name) describe the same physical outline, without the second, conflicting package that exists for the 8-lead case.

That’s worth stating plainly because this site’s own VSSOP reference documents a real, TI-acknowledged naming problem at 8 leads: TI uses “VSSOP” for both its DGK package (0.65 mm pitch, JEDEC MO-187 variation AA) and its DCU package (0.5 mm pitch, JEDEC MO-187 variation CA) — a mix-up with a documented real-world cost. No comparable second 10-lead “VSSOP” package turned up in this research. If you’re working from a part in DGS, you’re working with a single, consistently-defined outline.

Dimensions

Parameter	Value
Body (D × E1)	~2.9–3.1 mm × 2.9–3.1 mm (JEDEC MO-187 variation BA envelope)
Lead-tip span (E)	4.75–5.05 mm
Overall height (max)	1.1 mm
Lead pitch (e)	0.5 mm
Lead width (b)	0.17–0.27 mm
Package code	DGS (TI); JEDEC MO-187, variation BA

Real shipped parts land under that 1.1 mm ceiling, not at it — RS Components lists the TPL5000DGST timer IC at 3.1 × 3.1 × 0.95 mm, confirming the body-width figures above and showing an actual seated height comfortably inside the max spec.

Land Pattern

TI’s DGS0010A drawing includes an example land pattern (document 4221984/A):

Pad size: 1.45 mm (length) × 0.3 mm (width), 10 pads
Pad pitch: 0.5 mm, matching the lead pitch exactly
Symmetric span: 4.4 mm
Standard IPC-7351/IPC-7525 caveat applies: a fabrication site or CAD library may specify an alternate design; treat TI’s numbers as the verified starting point, not a mandate.

Don’t reuse an 8-lead VSSOP/MSOP land pattern for a 10-lead part — the pitch alone (0.5 mm vs. 0.65 mm on the common DGK-8/MSOP-8 outline) makes the pads land in the wrong places, on top of the different pad count and span.

Real Parts in This Package

VSSOP-10/DGS shows up across a genuinely wide range of TI analog and mixed-signal parts, not one narrow niche:

ADS1015 and ADS1013 — 12-bit, I2C-compatible ADCs
ADS1115 — 16-bit, I2C-compatible ADC
DAC8562 — 16-bit, dual-channel voltage-output DAC
TLV2373 — dual precision op-amp (also offered in 14-pin SOIC/PDIP for comparison)
TPL5000 — programmable timer/watchdog IC, common in low-power embedded designs

All are confirmed directly against TI’s own product pages, each independently labeling the package “VSSOP (DGS).”

Thermal Considerations

TI’s TLV2373/TLV2374 datasheet publishes real thermal data for the DGS-10 package alongside the same die in SOIC-14 and PDIP-14:

Thermal metric	DGS (VSSOP-10)	D (SOIC-14)	P (PDIP-14)
RθJA (junction-to-ambient)	166.5°C/W	67°C/W	66.3°C/W
RθJC, top (junction-to-case)	41.8°C/W	24.1°C/W	20.5°C/W
RθJB (junction-to-board)	86.1°C/W	22.5°C/W	26.8°C/W
RθJC, bottom	n/a	n/a	n/a

The small VSSOP-10 body runs meaningfully hotter for the same power dissipation than the larger SOIC-14 or PDIP-14 packages on the same die — a real trade-off for the space savings, not a free upgrade. The “n/a” on junction-to-case-bottom resistance across all three packages confirms none of them, including DGS, carries an exposed thermal pad.

What One Aggregator Gets Wrong

A distributor-facing package glossary describes “VSSOP (DGS)-10” as featuring “leadless design” and a “central thermal pad (80% coverage).” Neither claim holds up against TI’s own documentation. The DGS0010A drawing shows conventional gull-wing leads with a specified lead width and foot pattern — not a leadless QFN-style outline — and the real thermal data above lists junction-to-case-bottom resistance as not applicable across the board, which is exactly what you’d expect from a package with no exposed pad. If a source describes VSSOP-10 as leadless or thermally enhanced, don’t build a footprint from it without checking TI’s actual package drawing first.

VSSOP-10 vs. VSSOP-8 vs. MSOP-10

Attribute	VSSOP-10 (TI DGS)	VSSOP-8 (TI DGK)*	Generic MSOP-10
Body	~2.9–3.1 × 2.9–3.1 mm	~2.9–3.1 × 2.9–3.1 mm	~3.0 × 3.0 mm
Max height	1.1 mm	1.1 mm	1.1 mm
Lead pitch	0.5 mm	0.65 mm	0.5 mm
JEDEC	MO-187, variation BA	MO-187, variation AA	MO-187, variation BA
Naming ambiguity?	None found	Yes — TI’s DCU package also uses “VSSOP” for a different, finer-pitch outline	N/A (generic term)

*Full detail on the VSSOP-8/DGK-vs-DCU naming split, including a documented real-world design-revision case, is covered in this site’s dedicated VSSOP reference.

The same body footprint, a finer pitch to fit two more leads — the same pattern seen across this whole small-outline package family at other pin counts.

Soldering Notes

At 0.5 mm pitch, hand-soldering VSSOP-10 is meaningfully harder than the 0.65 mm-pitch packages most engineers cut their teeth on — doable with a fine-tip iron and flux for rework, but reflow with the verified land pattern above is the realistic path for production. Confirm MSL rating and reflow profile against the specific part’s datasheet before finalizing a stencil design, standard practice across this whole package family.

Selection Path

You have a specific TI part in DGS-10 → use the verified dimensions and land pattern above directly; no naming ambiguity to check against, unlike the 8-lead case.
You’re choosing between VSSOP-8 and VSSOP-10 for a new design → same body footprint either way; VSSOP-10 buys two more leads at a finer 0.5 mm pitch, a harder assembly process.
A datasheet or distributor listing claims VSSOP-10 has an exposed pad → verify against TI’s actual package drawing before trusting it; the thermal data doesn’t support that claim for DGS.
You’re laying out a footprint from scratch → pull TI’s DGS0010A land pattern directly rather than approximating one; the 0.5 mm pitch leaves little margin for error.

FAQ

What is the TI package code for VSSOP-10?

DGS. Confirmed directly against multiple current TI product pages (ADS1015, ADS1013, ADS1115, DAC8562, TPL5000), all labeling the package “VSSOP (DGS).”

What are the dimensions of a VSSOP-10 package?

Roughly 2.9–3.1 mm body on each side, 4.75–5.05 mm lead-tip span, 1.1 mm max height, 0.5 mm lead pitch — per TI’s DGS0010A package drawing, registered under JEDEC MO-187 variation BA.

What is the recommended VSSOP-10 land pattern?

TI’s own example uses 1.45 × 0.3 mm pads on 0.5 mm centers with a 4.4 mm symmetric span. Treat it as a verified starting point; your fabrication site or CAD library may specify an alternate per IPC-7351.

Does VSSOP-10 have an exposed pad?

No. TI’s own thermal data for the DGS package lists junction-to-case-bottom resistance as not applicable, consistent with no exposed pad, despite at least one distributor glossary claiming otherwise.

Is VSSOP-10 affected by the same naming confusion as VSSOP-8?

No comparable second 10-lead “VSSOP” package was found in this research. TI’s 8-lead VSSOP naming genuinely splits across two different packages (DGK and DCU); the 10-lead case does not show the same split.

What real parts use the VSSOP-10 package?

TI’s ADS1015 and ADS1013 (ADCs), ADS1115 (16-bit ADC), DAC8562 (DAC), TLV2373 (op-amp), and TPL5000 (timer) are all confirmed current parts in this package.

What to Do Next

Pull TI’s DGS0010A package and land pattern drawing directly rather than approximating one from a generic MSOP-10 template or an aggregator summary — the numbers above are sourced from it. Don’t assume an exposed pad based on secondhand descriptions; TI’s own thermal data doesn’t support that claim. And if you’re working from a different TI VSSOP part at 8 leads instead of 10, check which package code it actually uses (DGK or DCU) before reusing anything from this article.

External sources referenced

TI mpds035c.pdf (DGS0010A package/land pattern drawing) · TI product pages for ADS1015, ADS1013, ADS1115, DAC8562, TPL5000 · TI TLV2373/TLV2374 datasheet (thermal data) · RS Components listing for TPL5000DGST · this site’s VSSOP and uSOP references (JEDEC MO-187 cross-check)