Nearly every modern FPGA ships in a ball grid array. QFN and wafer-level parts exist, but they are reserved for the smallest, lowest-density devices. The hard part is the package code buried in the ordering number — FBG484, F23, SG48. This guide covers the FPGA package types you will meet, decodes the AMD, Intel, and Lattice naming schemes field by field, and gives you the pitch, thermal, and layout numbers that decide which package your board can actually build.
Key takeaways
- BGA dominates FPGAs. Anything above a few thousand logic cells is almost always a ball grid array; QFN shows up only on the smallest parts, such as the Lattice iCE40.
- The package code sits near the end of the part number. In XC7A100T-2FGG484C, FGG is the package and 484 is the ball count.
- AMD and Intel use different letters. AMD encodes construction and pitch (FF, FB, CS); Intel encodes body size (F, U, M), where the number is the body edge in millimetres, not the pin count.
- Pitch drives PCB cost. 1.0 mm routes with ordinary vias; 0.5 mm and finer usually forces HDI microvias and extra layers.
- Moisture matters. Most fine-pitch FPGA packages are MSL 3, giving 168 hours of floor life once the dry bag is opened.
The FPGA package types you’ll actually see
Three constructions cover almost the entire FPGA market, plus two edge cases worth knowing.
Ball grid array (BGA) and its variants
A BGA connects to the board through an array of solder balls under the package body instead of leads around the perimeter. That is why it scales to the pin counts FPGAs need: a 45 mm body can carry well over a thousand balls, which no peripheral-lead package approaches. FPGA datasheets show several sub-types:
- Wire-bond BGA (often called PBGA): the die is wire-bonded to an organic laminate substrate. Lower cost, used on smaller and mid-range parts.
- Flip-chip BGA (FCBGA): the die is flipped and bumped directly onto the substrate, shortening the interconnect and improving power delivery and signal integrity. The bumping and substrate make it more expensive than wire-bond, so it is reserved for high pin-count, high-performance FPGAs.
- Fine-pitch BGA (FBGA): the umbrella term for the 1.0 mm and finer ball pitches FPGAs use.
AMD’s 7-series, for example, splits its portfolio into wire-bond packages for lowest cost, conventional flip-chip for performance, and lidless (bare-die) flip-chip that trades a smaller body for high performance — a distinction most generic package guides never mention.
QFN, and why FPGAs rarely use it
A quad flat no-lead (QFN) package has pads on the underside edges and an exposed thermal pad in the centre, with no protruding leads. It is cheap, compact, and thermally strong for its size, which is why it dominates power and RF ICs. FPGAs use it only at the bottom of the density range. The clearest example is Lattice’s iCE40 UltraPlus: the ICE40UP5K-SG48I is a 5,280-LUT FPGA in a 48-pad QFN, 7 mm × 7 mm, 0.5 mm pitch, with an exposed pad, per the iCE40 UltraPlus datasheet. QFN does not scale because pads run only around the perimeter, so pin count is capped long before an FPGA’s I/O needs are met.
WLCSP and TQFP — the edge cases
Two more packages appear on small FPGAs. Wafer-level chip-scale (WLCSP) is essentially the bare die with balls, giving the smallest possible footprint; the same iCE40 UltraPlus offers a WLCSP around 2.15 mm × 2.55 mm at 0.4 mm pitch. At the other extreme, some low-density families still offer a leaded thin quad flat pack (TQFP) — the iCE40 LP/HX line goes up to a 20 mm × 20 mm TQFP — for engineers who want visible, hand-solderable joints.
[IMAGE 1: BGA solder-ball array beside a QFN with perimeter pads plus centre thermal pad — alt: “FPGA package types compared: BGA solder-ball array versus QFN pads and exposed thermal pad”]
Table 1. FPGA package families at a glance
| Package | Interconnect | Typical pitch | Pin range* | Thermal pad | Rework / inspection | Where it appears |
| Wire-bond BGA (PBGA) | Balls, wire-bonded die | 1.0 / 0.8 mm | ~150–700 | No (thermal balls) | X-ray; BGA rework | Small–mid FPGAs |
| Flip-chip BGA (FCBGA) | Balls, bumped die | 1.0 mm | ~500–2,000+ | No (balls / lid) | X-ray; BGA rework only | High-end FPGAs |
| QFN | Perimeter pads + exposed pad | 0.4–0.65 mm | ~30–100 | Yes | X-ray (hidden joints) | Smallest FPGAs / CPLDs |
| WLCSP | Balls on bare die | 0.35–0.4 mm | ~16–80 | No | X-ray; not practically reworkable | Ultra-small FPGAs |
| TQFP | Gull-wing leads | 0.4–0.5 mm | ~100–240 | Optional | Visible joints; hand-solderable | Legacy / small FPGAs |
*Pin ranges are typical, not hard limits; check the specific device-package table.
How to read the package code in an FPGA part number
An FPGA package code is the letter-and-number group near the end of the ordering number that names the package construction and size. The letters encode construction and ball pitch; the trailing number is the ball or pin count for AMD, or the body size for Intel. The two vendors do not share a scheme, so read them separately.
AMD (Xilinx) package designators
An AMD 7-series ordering code runs generation, family, size, speed grade, package, pin count, temperature. The package field is a construction letter pair. Per AMD’s 7-series product tables:
Table 2. AMD / Xilinx 7-series package codes
| Code | Construction | Ball pitch |
| CP | Wire-bond chip-scale | 0.5 mm |
| CS | Wire-bond chip-scale | 0.8 mm |
| FT | Wire-bond fine-pitch | 1.0 mm |
| FG | Wire-bond fine-pitch | 1.0 mm |
| SB | Lidless flip-chip | 0.8 mm |
| FB | Lidless flip-chip | 1.0 mm |
| FF | Flip-chip fine-pitch | 1.0 mm |
| FH / FL | Flip-chip | 1.0 mm |
| HC | Ceramic flip-chip | 1.0 mm |
The trailing letter also carries lead chemistry: G is RoHS with the exemption-15 lead-in-solder allowance, V is full RoHS. So FBG484 and FBV484 are the same 23 mm × 23 mm footprint with different solder chemistry.
Worked decode — XC7A100T-2FGG484C:
- XC — Xilinx commercial prefix
- 7 — series (7-series)
- A — family (Artix)
- 100T — ~100k logic cells, T variant
- -2 — speed grade (of -1, -2, -3; higher is faster)
- FG — wire-bond fine-pitch, 1.0 mm
- G — RoHS with exemption 15
- 484 — 484 balls, 23 mm × 23 mm body
- C — commercial, Tj 0 °C to +85 °C
Intel (Altera) package designators
Intel’s Altera families use a single family letter and — this is the trap — a number that is the body edge length in millimetres, not the pin count. Per the Cyclone V Device Overview, the letters are F (FineLine BGA / FBGA), U (Ultra FineLine BGA / UBGA), and M (Micro FineLine BGA / MBGA), with E (enhanced QFP) and Q (QFP) on older parts and V (WLCSP) on MAX 10.
Because the number is a body size, pin count depends on the family:
Table 3. Intel / Altera body-size code → ball count
| Family (letter) | Code = body size | Balls |
| FBGA (F) | 17 mm | 256 |
| FBGA (F) | 23 mm | 484 |
| FBGA (F) | 27 mm | 672 |
| FBGA (F) | 31 mm | 896 |
| FBGA (F) | 35 mm | 1,152 |
| UBGA (U) | 15 mm | 324 |
| UBGA (U) | 19 mm | 484 |
| MBGA (M) | 11 mm | 301 |
| MBGA (M) | 13 mm | 383 |
Worked decode — 5CEBA2U15C8N:
- 5C — Cyclone V family
- E — enhanced logic/memory feature set
- B — no hard PCIe / hard memory controller
- A2 — member (device-size code)
- U — UBGA (Ultra FineLine BGA)
- 15 — 15 mm body = 324 balls
- C — commercial, Tj 0 °C to +85 °C
- 8 — fabric speed grade (6 is fastest, 8 slowest)
- N — lead-free / RoHS
Read this before you compare parts: AMD and Altera number speed grades in opposite directions. On AMD 7-series, -3 is faster than -1. On Altera Cyclone, 6 is faster than 8. Reading an Altera part with Xilinx habits will make a fast device look slow.
Lattice and other vendors
Lattice uses its own pairs: SG for QFN (SG48 = 48-pad QFN), CM/CB for chip-scale BGA, and SWG/UWG for WLCSP. ICE40UP5K-SG48I decodes as iCE40 UltraPlus, 5K LUTs, SG (QFN), 48 pads, I (industrial). Microchip PolarFire and Intel Agilex use longer alphanumeric codes; always pull the ordering-information figure from the specific family datasheet rather than assuming a code carries across vendors.
[IMAGE 2: Annotated FPGA ordering number with each field labelled, package code field highlighted — alt: “How to read FPGA package codes: annotated part number showing the package field for BGA and QFN”]
Choosing a package — the decision path
Package choice is usually settled by four constraints, in this order: can your board route it, can it cool it, does it have the I/O you need, and can your line build it.
Pitch sets your PCB layer count and cost
Ball pitch is the single biggest cost driver. Fabricator rules of thumb:
- 1.0 mm: conventional through-vias and dog-bone fanout; routes on modest layer counts.
- 0.8 mm: dog-bone still works, but needs ~0.25 mm (10 mil) or narrower traces and deliberate planning.
- 0.65 mm: partial via-in-pad and a clear breakout plan.
- 0.5 mm and below: HDI territory — filled, plated microvia-in-pad with ~0.18–0.20 mm (7–8 mil) traces, often with blind/buried vias.
- 0.4 mm: HDI is effectively unavoidable.
Layout engineers estimate layer count with: layers ≈ (signal balls to route) ÷ (4 × routable rows per layer) + 1 for margin. A 484-ball 1.0 mm part fans out on far fewer layers than a 900-ball 0.8 mm part, and that gap shows up directly in board cost.
Table 4. Ball pitch → routing strategy
| Pitch | Fanout strategy | Via type | Typical trace | HDI needed? |
| 1.0 mm | Dog-bone | Through-via | ≤0.25 mm | No |
| 0.8 mm | Dog-bone | Through / blind | ~0.25 mm | Rarely |
| 0.65 mm | Partial via-in-pad | Blind / through | ~0.20 mm | Sometimes |
| 0.5 mm | Microvia-in-pad | Filled + plated microvia | 0.18–0.20 mm | Usually |
| 0.4 mm | Full via-in-pad | Stacked microvia | ≤0.18 mm | Yes |
Thermal
BGAs spread heat through the whole ball array and often add dedicated thermal balls or a lid; QFNs rely on the exposed centre pad soldered to a copper plane. For either package, the datasheet’s θJA and θJC values plus your airflow decide whether a heatsink is needed. Fine-pitch flip-chip FPGAs dissipating several watts usually need one.
I/O count and pin migration
Vendors design footprint-compatible packages so you can move up in density without re-laying the board — but only along defined migration paths. AMD notes migration is available within a family for like packages, not across families. Confirm the device-package table before assuming two parts drop into one footprint.
Assembly and rework capability
BGA and QFN joints are hidden under the body. Inspection needs X-ray, and rework needs hot-air or BGA rework stations, not an iron. If your line or prototype shop cannot do X-ray and BGA rework, that constraint alone can push you toward the coarsest-pitch option or a socketed evaluation board.
Package-driven mistakes that cause respins and returns
- Unfilled via-in-pad. An unfilled via in a QFN thermal pad or a fine-pitch BGA pad lets solder wick down the barrel during reflow, starving the joint and leaving voids or opens. Via-in-pad must be filled and plated over.
- Ignoring MSL floor life. Fine-pitch plastic packages absorb moisture; heat one past its floor-life window and trapped water flashes to steam, cracking the package (“popcorning”). This is a leading cause of latent BGA field failures.
- Assuming pin-compatibility. Two parts with the same ball count are not automatically footprint-compatible unless the migration table says so.
- Choosing 0.5 mm pitch without an HDI budget. If the board can only do through-vias, a 0.5 mm part cannot be escaped cleanly and the project stalls at layout.
Compliance and handling — MSL, RoHS, reflow
Moisture sensitivity level (MSL)
MSL, defined by IPC/JEDEC J-STD-020 and handled per J-STD-033, tells you how long a package can sit out of its dry bag before it must be reflowed or re-baked. Most fine-pitch BGA, QFN, and large QFP parts are rated MSL 3.
Table 5. MSL floor life (J-STD-033, ≤30 °C / 60% RH)
| Level | Floor life |
| 1 | Unlimited (at ≤30 °C / 85% RH) |
| 2 | 1 year |
| 2a | 4 weeks |
| 3 | 168 hours (7 days) |
| 4 | 72 hours |
| 5 | 48 hours |
| 5a | 24 hours |
| 6 | Bake before use; time per label |
The reflow reference for these ratings is a 260 °C peak. Exceed floor life and the fix is a bake, commonly 125 °C for parts rated for it. Check the specific FPGA datasheet — larger flip-chip BGAs are sometimes MSL 4.
RoHS in the part number
Lead chemistry is encoded in the ordering code, so you can read it without opening a datasheet. On AMD 7-series, V is full RoHS and G is RoHS with the exemption-15 allowance. On Altera, an N or G suffix marks lead-free / RoHS parts.
[IMAGE 3: BGA escape routing by pitch — dog-bone fanout at 1.0 mm next to microvia-in-pad at 0.5 mm — alt: “BGA escape routing by ball pitch: dog-bone fanout versus microvia-in-pad”]
FAQ
Do FPGAs come in QFN packages?
A few do. QFN is limited to the smallest, lowest-density FPGAs and CPLDs — for example the Lattice iCE40 UltraPlus in a 48-pad, 7 mm × 7 mm QFN. Mainstream and high-end FPGAs need hundreds to thousands of I/O, which only a ball grid array supplies, so anything above a few thousand logic cells is effectively BGA-only.
What does FBG mean in a Xilinx part number?
FBG is AMD/Xilinx shorthand for a lidless flip-chip BGA at 1.0 mm pitch, with the G marking RoHS with the exemption-15 lead allowance. The number after it is the ball count: FBG484 is 484 balls on a 23 mm × 23 mm body. The full-RoHS version of the same footprint is FBV484.
What is the difference between BGA and QFN?
A BGA connects through solder balls across the whole underside, scaling to very high pin counts with hidden joints that need X-ray inspection. A QFN uses pads only around the perimeter plus a centre thermal pad, so it is cheaper and lower-profile but capped near 100 pins. FPGAs use BGA for density and QFN only for their smallest parts.
How do I read an FPGA speed grade?
The speed grade sits just before the package field, and its direction depends on the vendor. AMD 7-series runs -1, -2, -3 with -3 fastest. Altera Cyclone runs 6, 7, 8 with 6 fastest. The two schemes point in opposite directions, so confirm the vendor before judging whether a part is fast.
What ball pitch do FPGA BGAs use?
Most FPGA BGAs use 1.0 mm or 0.8 mm pitch; the smallest chip-scale and wafer-level parts drop to 0.5 mm or 0.4 mm. Pitch matters more than pin count for your board: 1.0 mm routes with ordinary vias, while 0.5 mm and finer usually require HDI microvias and extra layers.
What is FBGA?
FBGA stands for Fine-pitch (or FineLine) Ball Grid Array — the general term for BGAs at 1.0 mm pitch and below, which is what almost every FPGA uses. Intel labels these with an F; Xilinx uses FB, FF, FG, and FT depending on construction and whether the die is wire-bonded or flip-chip.
What to do next
Start from the part number you are handed and the board you can build. Decode the package field first. If it is a 1.0 mm BGA (Xilinx FB/FF/FG, Intel F-series), any competent fabricator can route it. If it is 0.5 mm or finer, confirm your fab and assembler can do HDI microvias and X-ray before you commit — that check, not the logic-cell count, is what stalls FPGA boards. For a new design with real I/O needs, default to a 1.0 mm flip-chip BGA one pin-count step above your current requirement, verify the migration path in the device-package table, and confirm the MSL rating against your reflow profile. If your requirement is genuinely small and your line is BGA-averse, an iCE40-class QFN is the pragmatic escape.
