Post: Lattice FPGA Families, Specs, and Sourcing: The Complete Guide

Lattice FPGA devices are low-power, small-form-factor programmable logic chips aimed at edge AI, embedded vision, 5G, hardware security, and board control — not the million-LUT, data-center parts you buy from AMD or Altera. Lattice currently ships five active FPGA lines: the ultra-low-power iCE40, the cost-optimized ECP5, the 28 nm FD-SOI Nexus families (Certus-NX, CertusPro-NX, CrossLink-NX, plus the MachXO5-NX and Mach-NX control devices), and the 16 nm mid-range Avant platform. This guide maps each family to the job it actually does well, gives you the real numbers — logic cells, SERDES rates, memory, packages — and covers how to source and assemble these parts without losing a month to lead time, a batch to counterfeits, or a build to fine-pitch BGA defects.

Key takeaways

• Lattice’s sweet spot is low power and small size: densities run from ~384 LUTs (iCE40) up to ~637K logic cells (Avant), with SERDES from 3.2 Gbps (ECP5) to 25 Gbps (Avant-X).
• The 28 nm FD-SOI Nexus platform trades process node for physics — roughly 75% lower power and about 100x lower soft-error rate than a comparable bulk-CMOS process.
• iCE40 and ECP5 have mature open-source toolchains (Yosys + nextpnr); the Nexus and Avant families use Lattice Radiant.
• Package pitch drives board cost: anything below 0.65 mm usually forces via-in-pad, and 0.4 mm WLCSP effectively requires HDI.
• Buy through authorized channels and check lifecycle status — the counterfeit and obsolescence risk on programmable logic is real.

What Is a Lattice FPGA (and Where It Fits)

An FPGA — field-programmable gate array — is an integrated circuit whose logic you configure yourself, wiring up look-up tables (LUTs), flip-flops, block RAM, DSP multipliers, and I/O into whatever digital function you need, then reprogramming it when requirements change. A Lattice FPGA is one built by Lattice Semiconductor (NASDAQ: LSCC), a company that deliberately does not chase the high-density, high-power end of the market. Where AMD (Xilinx) and Altera fight over data-center accelerators with millions of logic elements and 58G-plus transceivers, Lattice optimizes for the opposite corner: microwatt-to-milliwatt power, packages a few millimeters on a side, instant-on configuration, and price points that let an FPGA sit next to an ASIC or MCU as a companion chip.

That positioning shapes where you actually see these parts: sensor and camera bridging (MIPI, LVDS, SLVS-EC), power-on control and hardware root-of-trust, motor and industrial I/O, always-on AI in wearables and laptops, and glue logic that patches an interface mismatch you found after the ASIC taped out. Lattice says it has shipped more than 50 million edge-AI devices, most of them small Nexus-based parts.

One thing to get straight before you compare datasheets: “logic cells” and “LUTs” are not the same currency. Lattice quotes “system logic cells” on its Nexus and Avant families — a normalized figure that rolls in LUTs plus a weighting for embedded memory and DSP. The native building block is still a 4-input LUT (LUT4). If you size a design against a competitor’s LUT6-based “logic element” count using Lattice’s headline logic-cell number, you can be off by a wide margin in either direction. Map your design to native LUT4s before you pick a part.

Lattice FPGA Families Compared: iCE40, ECP5, Nexus, and Avant

Here is the full active lineup at a glance, then the detail on each. Densities, SERDES rates, and packages are drawn from Lattice’s current product documentation.

Family	Process	Logic capacity	Max SERDES	Best-fit job
iCE40 LP / HX / UltraPlus	40 nm	384 – 7,680 LUTs	None	Always-on sensor and glue logic at the lowest power
ECP5 / ECP5-5G	40 nm	Up to 85K LUTs	3.2 / 5 Gbps (x4)	Low-cost SERDES bridging and small soft-CPU designs
MachXO2/3/4, MachXO5-NX, Mach-NX	65 nm / 28 nm FD-SOI	Up to ~9.4K LUTs (XO3); more on NX	None	Instant-on control, power sequencing, root-of-trust security
Certus-NX / CertusPro-NX	28 nm FD-SOI	Up to 100K logic cells	10.3 Gbps (x8)	General-purpose low-power with fast SERDES and LPDDR4
CrossLink-NX / CrossLinkU-NX	28 nm FD-SOI	Up to ~40K logic cells	MIPI D-PHY, multi-Gbps/lane	Embedded vision, sensor aggregation, display bridging
Avant-E / -G / -X	16 nm FinFET	Up to ~637K logic cells	12.5 / 25 Gbps (up to x28)	Mid-range compute, NICs, high-bandwidth edge systems

iCE40 — the ultra-low-power workhorse

The iCE40 line (LP, HX, and the feature-richer UltraPlus) is the smallest, cheapest, lowest-power FPGA Lattice makes. Densities run from 384 to 7,680 LUTs, with static current as low as ~75 µA on UltraPlus and active current in the single-digit-milliamp range for typical designs. There is no SERDES and no DDR controller — this is for always-on jobs: waking a system on a sensor event, bridging a camera’s MIPI or LVDS to a host, running a small neural-network IP for keyword or motion detection. UltraPlus adds up to ~1 Mb of single-port RAM (SPRAM) and DSP blocks for that light AI work. Packages get down to a ~2.5 mm WLCSP, which is why iCE40 shows up in phones and wearables where a few square millimeters decides the design.

ECP5 / ECP5-5G — cheap SERDES and small SoCs

ECP5 is the value SERDES part. On a 40 nm process it reaches up to 85K LUTs, 3.7 Mb of embedded RAM, 156 18×18 multipliers, and up to four SERDES channels at 3.2 Gbps (ECP5) or 5 Gbps (ECP5-5G, which is pin-compatible), with DDR3/LPDDR3, PCIe, Gigabit Ethernet, and 7:1 LVDS support. Lattice fits 85K LUTs plus SERDES into a 10×10 mm package, and a single SERDES channel starts below 0.25 W. It is a favorite for open-source RISC-V SoCs and low-cost video/networking bridges because it is big enough to hold a soft CPU and cheap enough to ship in volume.

MachXO and the control / security FPGAs

The MachXO family (XO2/XO3/XO4, plus the Nexus-based MachXO5-NX and the security-focused Mach-NX) is built for control, not compute. These are non-volatile: on-chip flash means they configure in about 1 ms (instant-on) and hold their configuration with no external boot PROM. That makes them the natural choice for board management — power sequencing, reset supervision, I/O expansion, fan and thermal control — and, on Mach-NX and MachXO3D, a hardware root-of-trust that authenticates firmware before the rest of the board powers up. If your FPGA job is really “be the first thing alive on the board and police everything else,” this is the family, and it quietly drops a config PROM off your BOM in the process.

The Nexus platform — Certus-NX, CertusPro-NX, CrossLink-NX

Nexus is Lattice’s 28 nm FD-SOI generation and the current volume workhorse. The platform claim is the interesting part: versus a comparable bulk-CMOS process, FD-SOI delivers roughly 75% lower power and about 100x lower soft-error rate (SER) — meaning far fewer configuration upsets from cosmic radiation, which matters in automotive, medical, and any long-uptime system. CertusPro-NX tops the general-purpose line: up to 100K logic cells, 7.3 Mb RAM, eight SERDES lanes at 10.3 Gbps, PCIe Gen3, 10G Ethernet, and — uniquely in its class — LPDDR4 support at 1066 Mbps, in packages as small as 9×9 mm. Certus-NX is the smaller sibling (PCIe Gen1/2, GbE) with roughly twice the I/O density per mm² of comparable parts and instant-on I/O in 3 ms. CrossLink-NX and the USB-equipped CrossLinkU-NX handle embedded vision — multi-gigabit MIPI D-PHY, sensor aggregation, and display bridging.

Avant — Lattice’s move into the mid-range

Avant is the newer 16 nm FinFET (TSMC) platform that pushes Lattice into territory long owned by mid-range Xilinx and Altera parts, roughly 100K to 637K logic cells. Three variants share the same fabric and differ in their hardened peripherals: Avant-E (up to 500K LC, 36 Mb RAM, SERDES to 25 Gbps, PCIe Gen4, LPDDR4/DDR5), Avant-G (up to 637K system logic cells, up to 28 SERDES lanes at 12.5 Gbps, PCIe Gen3 x8, DDR4), and Avant-X (the high-bandwidth part — up to 28 lanes of 25 Gbps SERDES, PCIe Gen4, DDR5). Lattice claims up to 2.5x lower power than competing mid-range FPGAs, which is the entire point: mid-range capacity at the power budget of a low-power vendor. Note the counterintuitive process story — Avant sits on a newer, smaller 16 nm node than Nexus’s 28 nm, yet it targets higher performance, not lower power. Nexus stays the low-power champion because FD-SOI’s programmable back-bias lets it trade leakage for speed on the same die; Avant buys density and bandwidth from the finer node.

How to Choose the Right Lattice FPGA for Your Design

Work the decision in this order — it will save you a re-spin:

1. Size the logic honestly. Translate your RTL into native LUT4s and required DSP/RAM, not the marketing logic-cell number. Add ~20-30% headroom for timing closure and late features.
2. Count your high-speed links. No SERDES needed goes to iCE40 or MachXO. A few links up to 5 Gbps goes to ECP5. 10G-class goes to CertusPro-NX. PCIe Gen4 or 25G goes to Avant-X. MIPI-heavy vision goes to CrossLink-NX.
3. Decide if you need instant-on / non-volatile. Flash-based parts (MachXO, iCE40, Certus-NX) boot in milliseconds and drop the external config PROM from your BOM. SRAM-only parts need a boot device and a boot-time budget.
4. Set the power and reliability bar. Battery or always-on leans iCE40/Nexus. Long-uptime or safety-relevant leans Nexus for its low SER. Automotive means confirming the AEC-Q100 grade (CertusPro-NX, Certus-NX, and others offer it).
5. Pick the toolchain you can live with. iCE40 and ECP5 give you an open-source flow; everything Nexus/Avant runs on Radiant (more on this below).
6. Only now choose a package. The smallest ball-pitch that fits is not automatically the cheapest board — see the assembly section next.

Designing and Assembling a Board Around a Lattice FPGA

This is where a datasheet win becomes a manufacturing problem, and where most “which Lattice FPGA” articles go quiet. Lattice’s whole pitch is small packages, and small packages mean fine-pitch BGAs and wafer-level chip-scale parts that your PCB and your assembly process have to actually support.

Fine-pitch BGA and WLCSP escape routing

Ball pitch drives your whole stack-up and your fab cost. Use this as a field guide, and check it against the device’s specific ball count:

Ball pitch	Escape-routing approach	Board technology
0.8 mm and up	Standard dog-bone escape to through-vias	Conventional 4-6 layer
0.65 mm	Dog-bone with fine lines/spaces; careful via placement	Conventional, tight design rules
0.5 mm	Via-in-pad (filled and plated over) – no room for dog-bone	Via-in-pad, often sequential lamination
0.4 mm / WLCSP	Laser microvias plus via-in-pad, effectively mandatory	HDI (microvia build-up)

Here is the trade-off engineers miss: choosing the 0.5 mm WLCSP to save 10 mm² of board area can add more to PCB fabrication cost — via-in-pad, sequential lamination, laser microvias — than you ever saved on the device or the real estate. Size the package to the board budget, not just the enclosure.

A real example from the line: a vision client picked a 0.5 mm-pitch CertusPro-NX to shrink a camera module, laid it out on a standard 4-layer stack with dog-bone vias, and watched first-pass BGA yield fall off from voids and opens on the inner ball rows. The fix was via-in-pad with filled-and-capped microvias plus a stencil aperture change to control paste volume — a board respin and a new stencil, caught only because X-ray inspection flagged the inner-ball voiding. A DFM review before fab would have specified via-in-pad from the start. Design and assembly of area-array parts like these is exactly what IPC-7095 exists to cover.

Two more assembly realities for these parts. First, moisture sensitivity: fine-pitch BGA and WLCSP FPGAs are typically MSL 3 under J-STD-020, so reels have a limited floor life once the dry bag is opened — exceed it and you must bake before reflow or risk popcorning and head-in-pillow defects. Check the specific device’s MSL rating. Second, inspection: you cannot see BGA joints, so acceptance leans on X-ray and AOI, graded to IPC-A-610 Class 2 for most commercial gear or Class 3 for high-reliability, with soldering held to J-STD-001.

Impedance-controlled stack-up for high-speed SERDES

The moment you use a SERDES lane above roughly 5 Gbps — CertusPro-NX at 10.3 Gbps, Avant-X at 25 Gbps — laminate and stack-up stop being a formality. You need controlled impedance (50 Ω single-ended, 100 Ω differential) with tolerance held to ±10% or tighter, reference planes directly under the pairs for a clean return path, and back-drilling of via stubs on the fastest lanes.

Material matters more than most BOMs admit. Standard FR-4 has a dissipation factor (Df) around 0.02 and runs on the order of 0.8-1 dB/inch of insertion loss up near 10 GHz. A low-loss laminate — Panasonic Megtron 6, an Isola low-loss system, or a PTFE/ceramic Rogers 4350B — drops Df to roughly 0.002-0.004 and insertion loss toward ~0.3 dB/inch. Over a short CertusPro-NX 10G link on a small board, good mid-loss FR-4 may be fine; push an Avant-X 25G lane across any real distance and you will want the low-loss stack or the eye closes. That is a direct cost-versus-performance call, and it is far cheaper to make it before layout than after a failed compliance test.

Lattice FPGA Sourcing, Stock, and Lead Times: Authorized vs Independent

Getting the right part on your board starts with buying it from the right place. Lattice sells through a network of authorized distributors — Arrow, Avnet, DigiKey, Mouser, and Future Electronics among them — plus its own online store and regional sales offices. Authorized stock is traceable to Lattice, which is the single biggest thing standing between you and a counterfeit or re-marked part.

That risk is not theoretical for programmable logic. FPGAs are high-value, long-lifecycle parts, which makes them a favorite target for gray-market re-marking and recycled-device fraud. When a listing’s price looks too good, or “in stock now” appears for a part everyone else has on a 40-week lead time, treat it as a red flag, not a bargain. Lattice’s SupplyGuard program exists specifically to give secure, traceable supply for security- and safety-critical builds.

A few sourcing realities to plan around:

• Lead times swing hard. Programmable logic has seen everything from stock-on-shelf to a year of lead time within one cycle; design in a second-source package option where you can, and place long-lead orders early.
• Lifecycle status is a spec. Older parts (early MachXO, ECP3, some ispMACH devices) move to mature or NRND status and eventually to last-time-buy; Lattice routes end-of-life supply through Rochester Electronics. Check the lifecycle before you design a part into a 10-year product.
• Reels, MSL, and date codes matter for assembly. A cheap tray of loose parts with an unknown date code and a broken moisture bag can cost you more in yield than you saved on unit price.

This is where an EMS partner earns its keep. We are not an authorized franchise distributor — we source through authorized channels and vetted suppliers as part of turnkey PCBA, verify date codes and lifecycle status, handle MSL-controlled parts correctly, and build the board. Send a bill of materials (Gerber or ODB++ for the layout), and the useful questions we answer are “can this be sourced authorized, at this volume, in this timeframe” and “will this package build at the yield you need” — before you commit.

Lattice FPGA Design Software and Open-Source Toolchains

Which software you use depends entirely on the family:

• Lattice Radiant is the current tool for Nexus (Certus-NX, CertusPro-NX, CrossLink-NX, MachXO5-NX) and Avant.
• Lattice Diamond is the older environment for ECP5, MachXO2/3, and earlier parts.
• Lattice Propel adds the embedded/SoC flow for building RISC-V-based systems in the fabric.
• iCEcube2 is the legacy iCE40 tool, largely superseded by Radiant for UltraPlus.

The differentiator few vendors can match: Lattice’s smaller parts have a mature, fully open-source toolchain. Project IceStorm (iCE40), Project Trellis (ECP5), and Project Oxide (Nexus) document the bitstream formats, while Yosys handles synthesis and nextpnr does place-and-route — a complete, license-free Verilog-to-bitstream flow that runs on Linux and is reproducible in CI. For iCE40 and ECP5 this flow is genuinely production-viable and is a big reason those parts dominate open hardware. The catch: open tooling trails the newest silicon and lacks some of the vendor timing-closure and IP conveniences, so weigh reproducibility and zero license cost against feature completeness.

Common Lattice FPGA Design and Assembly Mistakes

The ones we see bite real projects:

1. Sizing against “logic cells” instead of native LUT4s, then running out of fabric late in the schedule.
2. Choosing the smallest package for the enclosure and discovering it forces HDI you never budgeted for.
3. Routing a >5 Gbps SERDES on standard FR-4 with no controlled impedance, then failing compliance.
4. Forgetting the return path — breaking a reference plane under a differential pair and radiating EMI.
5. Skipping via-in-pad on a 0.5 mm-pitch BGA and getting voids, opens, or head-in-pillow joints.
6. Ignoring the MSL rating — leaving parts out past floor life and popcorning them in reflow.
7. Designing in an NRND or mature device for a long-life product without checking lifecycle.
8. Buying from an unvetted broker to dodge lead time, then chasing counterfeits through field returns.

Do these on Monday: pin down your real LUT4 budget; decide instant-on versus external-boot early; set the SERDES stack-up (impedance and laminate) before layout; confirm each part’s lifecycle status and MSL; and get a DFM review on the footprint and stack-up before you release to fab.

Frequently Asked Questions About Lattice FPGAs

Which Lattice FPGA family should I use?

Match the family to the workload: iCE40 for ultra-low-power always-on and glue logic, ECP5 for cheap SERDES and small soft-CPU designs, MachXO for instant-on control and security, Certus/CertusPro-NX for general-purpose low-power with fast SERDES, CrossLink-NX for vision, and Avant for mid-range compute and high-bandwidth links.

Are Lattice FPGAs good for beginners and open-source projects?

Yes. The iCE40 and ECP5 families have the most mature open-source FPGA toolchain available (Yosys, nextpnr, Project IceStorm and Trellis). Cheap boards like the iCEstick and iCEBreaker plus a license-free, reproducible flow make Lattice the default entry point for hobbyists and open-hardware developers.

How do Lattice FPGAs compare to AMD (Xilinx) and Intel (Altera)?

Lattice competes on low power, small size, instant-on, and cost, not raw capacity. It tops out around 637K logic cells (Avant); if you need millions of LUTs, HBM, or 58G-plus transceivers, that is AMD Versal or Altera Agilex territory. For control, bridging, vision, and power-efficient edge logic, Lattice usually wins.

What is the Lattice Nexus platform?

Nexus is Lattice’s 28 nm FD-SOI FPGA platform underpinning the Certus-NX, CertusPro-NX, CrossLink-NX, and MachXO5-NX/Mach-NX families. Its FD-SOI process delivers roughly 75% lower power and about 100x lower soft-error rate than comparable bulk-CMOS parts, which is why it dominates automotive and long-uptime designs.

What software do I need to program a Lattice FPGA?

Use Lattice Radiant for Nexus and Avant parts, Lattice Diamond for ECP5 and MachXO2/3, and Lattice Propel for embedded RISC-V designs. For iCE40 and ECP5 you can instead use the open-source Yosys + nextpnr flow, which is free and needs no vendor license.

Are Lattice FPGAs automotive-qualified?

Several are. CertusPro-NX, Certus-NX, and other families offer AEC-Q100-qualified grades, and the Nexus platform’s low soft-error rate suits functional-safety systems. Always confirm the specific part number’s temperature grade and qualification in its datasheet before you design it in.

Where can I buy Lattice FPGAs and check stock?

Buy through authorized distributors — Arrow, Avnet, DigiKey, Mouser, Future Electronics — or Lattice’s online store, and check stock and lifecycle status on each. For production builds, an EMS partner can source authorized parts as part of turnkey assembly and verify date codes and MSL handling.

Getting Your Lattice FPGA Design Built Right

Picking the right Lattice FPGA is half the job; getting it onto a board at yield is the other half — the package pitch, the SERDES stack-up, the MSL handling, and the sourcing all decide whether your design ships on time. If you have settled on a family, send us your Gerber and BOM for a free DFM review and a sourcing-plus-assembly quote, and we will flag the footprint, stack-up, and supply risks before they cost you a respin.