A DIP package (dual in-line package) is a through-hole IC housing with two parallel rows of leads on a 2.54 mm (0.1 in) pitch. Row spacing is normally 7.62 mm or 15.24 mm, per JEDEC MS-001 and MS-011. Lead counts run from 4 to 64. No current FPGA is offered in DIP.
Key specifications at a glance
| Parameter | Value |
| Lead pitch | 2.54 mm (0.100 in). Shrink DIP: 1.778 mm. Soviet-era metric parts: 2.5 mm |
| Row spacing / JEDEC outline | 7.62 mm → MS-001 · 10.16 mm → MS-010 · 15.24 mm → MS-011 · 22.86 mm (ceramic side-brazed) |
| Lead count | 4 to 64. Always even. ~64 is the practical ceiling |
| Mounting | Through-hole. Wave, selective or hand solder. Socketable, including ZIF |
| Land-pattern standard | IPC-7251 (NOT IPC-7351, which is surface mount) |
| Hole / land sizing | IPC-2222 / IPC-2221. Worked example: 0.90 mm drill, 1.50 mm land (padstack C150H90) |
| Moisture sensitivity (MSL) | Not applicable. J-STD-020 is scoped to surface-mount devices |
| Variants | PDIP · CDIP / CERDIP · Windowed CERDIP · SDIP (shrink) · SPDIP · MDIP |
| FPGA availability | None. No vendor ships an FPGA in DIP. Programmable logic in DIP stops at SPLD |
Sources: JEDEC JEP95 (MS index); IPC-7251; IPC-2221/2222; IPC/JEDEC J-STD-020 (scope). Full source list in Appendix B.
Key takeaways
- Lead pitch is always 2.54 mm — except Shrink DIP, at 1.778 mm, and Soviet-era metric parts, at 2.5 mm.
- Row spacing tells you the JEDEC outline: 300 mil → MS-001, 400 mil → MS-010, 600 mil → MS-011.
- A 24-pin DIP is not always 600 mil. Read the package code, not the pin count.
- MSL does not apply. J-STD-020 is scoped to surface-mount devices.
- The land-pattern standard is IPC-7251, not IPC-7351.
- No FPGA ships in a DIP. Programmable logic in a genuine DIP stops at the SPLD class.
What a DIP package is, and how to read one
A DIP is an IC housing with a rectangular body and two parallel rows of leads that pass through holes in the board, or plug into a socket. Engineers at Fairchild — Don Forbes, Rex Rice and Bryant Rogers — created the format in 1964, when round transistor-style cans had run out of leads for increasingly complex integrated circuits. The first parts had 14 leads and looked much like they do now.
The naming convention is DIPn, where n is the total lead count: DIP14, DIP16, DIP40. A width suffix is sometimes appended — N for the narrow 0.3 in body, W for the wide 0.6 in body. Where no width is given, assume 0.3 in.
Lead counts are always even. Where the die needs an odd number of connections, the package carries a not-connected (NC) lead, or duplicates a ground.
Pin 1 sits at the top left when the body’s notch or dimple is at the top; numbering then runs counter-clockwise. On a 14-lead DIP the left column is 1–7 top to bottom and the right column is 8–14 bottom to top. On parts where leads are physically absent — LED bar displays, relays, packages with a heatsink fin — the remaining leads are still numbered as if every position were populated.
Inside, a tin-, silver- or gold-plated lead frame supports the die; fine bond wires connect the die pads to the lead fingers; an epoxy mould compound (or a ceramic lid) encapsulates the assembly. Plastic DIPs are not hermetic — the mould compound is somewhat porous to moisture — while ceramic DIPs are. That is why high-reliability parts and UV-erasable EPROMs use ceramic.
DIP dimensions: pitch, row spacing and the JEDEC outlines
Lead pitch on a standard DIP is 2.54 mm (0.100 in) and does not vary. What varies is row spacing — the distance between the two lines of holes — and that is what the JEDEC registration number tells you.
Table 1 — DIP row spacings and their JEDEC outlines
| Row spacing | JEDEC outline | Lead pitch | Typical lead counts | Less common | Example |
| 7.62 mm (0.300 in) | MS-001 | 2.54 mm | 8, 14, 16, 20 | 4, 6, 18, 24, 28 | ATF22V10C-15PU (24-lead, 24P3) |
| 10.16 mm (0.400 in) | MS-010 | 2.54 mm | — | rarely specified | — |
| 15.24 mm (0.600 in) | MS-011 | 2.54 mm | 24, 28, 32, 40 | 36, 42, 48, 52, 64 | Motorola 68000 (64-lead) |
| 22.86 mm (0.900 in) | ceramic side-brazed family | 2.54 mm | 50, 64 | — | large ceramic microprocessors |
| 7.62 / 15.24 / 19.05 mm | Shrink DIP | 1.778 mm | 42, 64 | — | Microchip 64-lead Shrink PDIP, 750 mil body |
Source: JEDEC JEP95, Microelectronic Standard Outlines (MS) index. Cross-checked against Analog Devices package outline N-16 (compliant to JEDEC MS-001-BB), Microchip Packaging Specification DS00049 (rev. BE), and the Microchip ATF22V10C datasheet (doc0735). Lead-count conventions are observed practice across vendor catalogues, not a JEDEC-registered constraint.
One historical trap worth knowing: Soviet and Eastern-bloc parts used a metric 2.5 mm pitch rather than 2.54 mm. Over a 40-lead body that is 19 pitches, so the cumulative error is about 0.76 mm — enough to fight a Western socket at the far end of the row.
Why lead count alone doesn’t tell you the row spacing
Engineer’s note: Row spacing is the number that bites. A 24-lead DIP is usually 15.24 mm (0.600 in) — but Microchip’s ATF22V10C-15PU, the part most people actually buy today when they need a 22V10, is 24-lead at 7.62 mm (0.300 in). Microchip’s own datasheet calls that package 24P3: 24-pin, 0.300 in wide, PDIP. Lay the board out for a 600-mil footprint and the part will not go in. Read the package code, not the pin count.
DIP package types: PDIP, CDIP, SDIP and SPDIP
Table 2 — DIP variants
| Variant | Full name | Body | Lead pitch | Typical row spacing | Hermetic | Where you still see it |
| PDIP | Plastic dual in-line package | Moulded epoxy | 2.54 mm | 7.62 / 15.24 mm | No | The default. Logic, op-amps, 8-bit MCUs, SPLDs |
| CDIP / CERDIP | Ceramic dual in-line package | Ceramic, sealed | 2.54 mm | 7.62 / 15.24 mm | Yes | Military and high-temperature parts; MIL-STD-883 Class B flows |
| Windowed CERDIP | Ceramic DIP with quartz window | Ceramic | 2.54 mm | 7.62 / 15.24 mm | Yes | UV-erasable EPROMs |
| SDIP (shrink) | Shrink dual in-line package | Plastic | 1.778 mm | 7.62 / 15.24 / 19.05 mm | No | High-lead-count MCUs (e.g. 64-lead, 750-mil body) |
| SPDIP (Microchip usage) | “Skinny” plastic dual in-line package | Plastic | 2.54 mm | 7.62 mm | No | 24- and 28-lead parts in a narrow body |
| MDIP | Moulded dual in-line package | Plastic | 2.54 mm | as PDIP | No | Synonym for PDIP in some vendor documents |
Source: JEDEC JEP95 (MS index); Microchip Packaging Specification DS00049 (rev. BE); Wikipedia, Dual in-line package (corroborating, for the SDIP/SPDIP naming ambiguity).
Ceramic is not just a heat story. It is the hermetic story: a sealed ceramic cavity keeps moisture out permanently, which is why the military and UV-EPROM parts live there. Plastic is cheaper by an order of magnitude — one 1979 study put a plastic 14-lead DIP at about US$0.063 against US$0.82 for the ceramic equivalent.
The SPDIP trap: same four letters, two pitches
SDIP and SPDIP each have two meanings in current use, and they differ by a factor of 1.43 in lead pitch. Get it wrong and your footprint is unbuildable.
- Reading A (JEDEC / general industry): SPDIP = Shrink Plastic DIP. Lead pitch 1.778 mm (0.070 in).
- Reading B (Microchip): SPDIP = Skinny Plastic DIP. Normal 2.54 mm pitch, narrow 300-mil body. Microchip’s Packaging Specification DS00049 lists, in as many words, a 24-lead Skinny Plastic Dual In-Line (SP) — 300 mil body — and brackets it as [SPDIP].
And it gets worse inside a single vendor. Microchip’s ATF22V10C datasheet calls the 24-lead package 24P3 — a 24-pin, 0.300 in wide PDIP. Microchip’s own product change notice for the same ordering code describes it as a 24L SPDIP (.300 in) package. Same silicon, same body, same vendor, two names.
While we are here: several of the top-ranking “DIP guide” pages claim that Shrink DIP delivers “six times the pin density” of a standard DIP. It does not. Going from 2.54 mm to 1.778 mm is a 1.43× increase in leads per unit length. The same pages list DIP pitches of 0.5 mm, 0.65 mm and 1.27 mm — those are SMD pitches, and no DIP has ever used them.
Engineer’s note: Never take a package abbreviation from a search result, a distributor attribute field or a BOM line. Take it from the vendor’s package drawing, and read the pitch dimension with your own eyes. Only two numbers matter — lead pitch and row spacing. Everything else is nomenclature.
How to decode a DIP part number
Package, speed and temperature grade are all encoded in the ordering code, and the vendor’s own ordering-information table is the only place to decode it. Here is the anatomy of the most commonly bought programmable DIP part on the market today:
ATF22V10C – 15 P U
| | | |
| | | +— lead finish / RoHS variant
| | +——- package: P = Plastic DIP (PDIP), datasheet code 24P3
| +———– speed: 15 ns propagation delay (tPD)
+———————— device: EE CMOS SPLD, 10 output logic macrocells
Table 3 — Ordering-code decoder: ATF22V10C-15PU
| Field | Value in this part | What it means | Other values you may see |
| Device | ATF22V10C | Microchip (Atmel) EE CMOS SPLD, 10 output logic macrocells | ATF22LV10C (3.3 V) · ATF22V10CQ / CQZ (low power) · ATF750C / ATF750CL |
| Speed | -15 | tPD = 15 ns (tS = 10 ns, tCO = 8 ns) | -5, -7, -10 |
| Package | P | Plastic dual in-line package. Datasheet package code 24P3 = 24-pin, 0.300 in wide PDIP | G / D → CERDIP (24D3) · J → PLCC (28J) · S → SOIC (24S) · X → TSSOP (24X) · N → ceramic LCC (28L) |
| Lead finish | U | Appears on both PDIP (-15PU) and PLCC (-15JU) codes, so it is NOT the package field. Microchip does not decode it in the datasheet’s ordering table — confirm with the vendor before committing a BOM line | X (e.g. ATF22V10C-7PX) |
| Temperature | (set by the ordering line) | Industrial, −40 °C to +85 °C | Commercial · Military −55 °C to +125 °C, e.g. ATF22V10C-15GM/883 in CERDIP, MIL-STD-883 Class B, DSCC SMD 5962-8984115LA |
Source: Microchip (Atmel) ATF22V10C / ATF22V10CQ / ATF22V10CQZ datasheet, document doc0735 — “Ordering Information” and “Package Type” sections; Microchip Packaging Specification DS00049 (rev. BE).
Worked examples across three vendors
Texas Instruments. TI’s PDIP package designator is N; a 20-pin PDIP appears in TI’s own device-marking documentation as “20 PIN PDIP (N)”. Some older CMOS logic uses E instead — CD74HCT02E is a 14-lead PDIP.
Microchip PIC/AVR. (P) is PDIP; (SP) is the 300-mil skinny body. The PIC16F59 is offered in PDIP (P) and TQFP (PT); the PIC16F1713 in 28-lead SPDIP. Microchip’s packaging spec also uses (PG), (PI) for 600-mil PDIPs and (PF), (PJ) for 300-mil skinny bodies — same package family, four more letters.
The rule: package letters are vendor-private. There is no cross-vendor package-code standard. JEDEC standardises the outline; the vendor invents the letter.
PCB design: land pattern, hole size and soldering
The land-pattern standard for a DIP is IPC-7251 (through-hole), not IPC-7351 (surface mount). Hole and land diameters come from IPC-2222 and IPC-2221. Here is the full calculation, worked.
- Take the maximum lead dimensions from the vendor’s package drawing. A typical 300-mil PDIP lead is up to about 0.56 mm wide and 0.38 mm thick. Check your part — these vary between vendors for the same nominal package.
- A DIP lead is rectangular, so use the diagonal as the effective maximum lead diameter: √(0.56² + 0.38²) ≈ 0.68 mm.
- Minimum hole = max lead diameter + 0.25 / 0.20 / 0.15 mm for IPC-2222 density Level A / B / C. At Level B: 0.68 + 0.20 = 0.88 mm → a 0.90 mm drill.
- Land diameter = minimum hole + 0.10 mm + 0.60 / 0.50 / 0.40 mm for IPC-2221 Level A / B / C. At Level B: 0.88 + 0.10 + 0.50 = 1.48 mm → a 1.50 mm land.
- In IPC padstack notation that is C150H90 — a 1.50 mm circular land with a 0.90 mm hole.
IPC-7251’s footprint naming convention is DIP + lead span + W lead width + P pitch + L body length + H height + Q pin quantity. A 14-lead 300-mil DIP therefore comes out as DIP762W52P254L1905H508Q14. Level B land patterns are explicitly suitable for wave, dip, drag or reflow soldering.
Table 4 — Mechanical and land-pattern data, 300-mil PDIP (worked)
| Parameter | Value | Source |
| Lead pitch | 2.54 mm (0.100 in) BSC | JEDEC MS-001 |
| Row spacing, shoulder to shoulder (E) | 7.62 mm nominal | Vendor package drawing |
| Moulded body width (E1) | 6.35 mm nominal | Microchip DS00049 |
| Max lead width (B) | ≈ 0.56 mm | Vendor package drawing |
| Max lead thickness (c) | ≈ 0.38 mm | Vendor package drawing |
| Effective max lead diameter | ≈ 0.68 mm (diagonal) | Derived |
| Minimum hole, IPC-2222 Level B | 0.88 mm → 0.90 mm drill | IPC-2222 |
| Land diameter, IPC-2221 Level B | 1.48 mm → 1.50 mm | IPC-2221 |
| Padstack | C150H90 | IPC-7251 / IPC-7351 padstack naming |
| Land-pattern standard | IPC-7251 | IPC |
| Assembly process | Wave, selective or hand solder | IPC-7251 Level B |
| Moisture sensitivity level | Not applicable — see below | IPC/JEDEC J-STD-020 (scope) |
Source: IPC-7251, Generic Requirements for Through-Hole Design and Land Pattern Standard; IPC-2221 / IPC-2222 (hole and land calculation); Microchip Packaging Specification DS00049 (rev. BE); Analog Devices package outline N-16 (compliant to JEDEC MS-001-BB). Re-derive against the drawing for your exact part.
Why MSL and reflow profiles don’t apply to DIP
J-STD-020 is titled Moisture/Reflow Sensitivity Classification for Nonhermetic Surface Mount Devices. The standard gives its own reasoning: in reflow, the solder operation happens on the same side of the board as the device, whereas in through-hole assembly the solder is applied under the board, which shields the component body from the heat. J-STD-033, which governs dry-pack, floor life and bake, is written for reflow, and does not apply to wave or selective soldering.
The practical consequences:
- A PDIP does not carry a meaningful MSL and does not need dry-pack, floor-life tracking or a pre-bake before wave soldering.
- The exception is pin-in-paste (intrusive reflow), where a through-hole part is passed through a reflow oven. If you are doing that, treat the part as surface mount and get a moisture-sensitivity commitment from the vendor in writing.
- MSL rules are also explicitly not written for hand soldering or rework — though local temperatures during rework can approach reflow, so use judgement on large ceramic bodies.
Engineer’s note: Nearly every “DIP package” guide on the first page of Google prints a moisture-sensitivity row in its spec table. That row was copied from a surface-mount template. Read the scope statement on the cover of J-STD-020 and you will find the standard excluding your part in its own title.
DIP vs SOIC vs SMD: when a DIP is still the right call
Choose a DIP when the part must be removable, socketable, hand-assembled, field-replaceable, or programmed off-board. Choose surface mount for everything else.
The SOIC is, structurally, a shrunk PDIP: the same gull-wing lead, bent a second time so that it lies flat on the board instead of passing through it. SOIC pitch is 1.27 mm — exactly half a DIP. SOP is 0.635 mm, a quarter.
| DIP | SOIC | |
| Lead pitch | 2.54 mm | 1.27 mm |
| Mounting | Through-hole | Surface mount |
| Board area | Large; needs drilled, plated holes | Small; no drilling |
| Socketable | Yes, including ZIF | Rarely |
| Parasitic lead inductance | Higher | Lower |
| Suitability at speed | Poor | Better |
| Practical lead-count ceiling | ~64 | Far higher |
| Moisture handling | No MSL, no dry-pack | MSL per J-STD-020 |
| Hand rework | Trivial | Needs skill and tools |
Source: JEDEC JEP95; IPC/JEDEC J-STD-020 (scope); Wikipedia, Dual in-line package (SOIC as a shrunk PDIP; DIP64 lead-length limitation).
You will find pages claiming that DIP has lower parasitic inductance than a small SMD package. It does not. Inside a large DIP the lead frame fans out radially from the die to the package perimeter and then runs down a 3 mm leg — a long current loop. That is exactly why the 64-lead DIP was the end of the road: the Motorola 68000’s DIP64 has internal leads so long that the package is unsuitable for high-speed parts.
That same geometry explains the ~64-lead ceiling. The leads must fan out radially, in a single plane, from the die perimeter to two rows on the package edge. More leads means a wider body, which means longer internal leads. Four-sided packages (QFP) and area arrays (PGA, BGA) exist precisely because the DIP ran out of road.
Programmable logic in DIP — and why there is no DIP FPGA
You cannot buy an FPGA in a DIP package. Not from AMD/Xilinx, not from Altera, not from Lattice, Microchip, GOWIN or Efinix. Current FPGA and CPLD families ship in QFP, QFN, CSP and BGA. Programmable logic in a genuine DIP stops at the SPLD class.
The reason is the ceiling above. An FPGA needs far more than 64 leads once you add user I/O, multiple core and I/O supply rails, ground returns and configuration pins — and the DIP’s lead inductance is unusable at FPGA clock rates.
What you can actually do:
- Buy an SPLD. The GAL/PAL class is still manufactured in 24-lead, 300-mil PDIP.
- Buy an FPGA on a DIP-form-factor carrier. Digilent’s Cmod A7 puts an Artix-7 on a 48-pin DIP-form-factor module — 44 digital FPGA I/O plus two analog inputs routed to 100-mil-spaced through-hole pins, 0.7 in × 2.75 in, so it drops into a breadboard or a standard socket. The Cmod S7 does the same with a Spartan-7 (48-pin form factor, 36 populated). Community boards do it too: a Lattice MachXO2-1200HC on a DIP-20-compatible carrier with 18 GPIO and a 6-pin programming header.
- Accept that a carrier is not a package. A module is a small PCB with headers. It will not survive a wave-solder pot, it carries its own regulators and configuration flash, and swapping a DIP part for one is a [FUNCTIONAL] substitution — never a drop-in.
Table 5 — Programmable logic you can actually get in a DIP
| Device | Vendor | Class | DIP option | Lifecycle | Notes |
| ATF22V10C | Microchip | SPLD, 10 macrocells | 24-lead 300-mil PDIP (24P3) | Active | Pin-to-pin and JEDEC-fusemap compatible with GAL22V10 |
| ATF22V10CQ / CQZ | Microchip | SPLD | 24-lead 300-mil PDIP | Active | Low-power and zero-power variants |
| ATF22LV10C | Microchip | SPLD | 24-lead 300-mil PDIP | Active | 3.3 V part — not a 5 V drop-in |
| ATF750C / ATF750CL / ATF750LVC | Microchip | SPLD | 24-lead 300-mil SPDIP | Active | Higher macrocell count |
| GAL22V10D | Lattice | SPLD | 24-lead DIP | Discontinued — last shipment June 2011 | No pin-compatible Lattice replacement offered |
| Any current FPGA or CPLD | AMD/Xilinx, Altera, Lattice, Microchip, GOWIN, Efinix | FPGA / CPLD | None | — | QFP / QFN / CSP / BGA only. Use a carrier module. |
Source: Microchip ATF22V10C datasheet (doc0735) ordering information; Microchip product change notice covering ATF22V10C, ATF22LV10C, ATF750C, ATF750CL and ATF750LVC in the 24-lead SPDIP (0.300 in) package; Lattice GAL22V10 discontinuation record; Digilent Cmod A7 / Cmod S7 reference manuals. FPGA/CPLD package availability checked against current vendor package options — re-verify before design-in.
Lifecycle, EOL and alternates for DIP parts
DIP is where lifecycle risk lives. The die is often decades old, the package is expensive to run at low volume, and the DIP option is almost always the first one a vendor drops.
Read the vendor’s own status field and act on it. Texas Instruments, for example, publishes: ACTIVE (recommended for new designs), NRND (in production for existing customers, not recommended for new designs), LIFEBUY (discontinued; a last-time-buy window is open), PREVIEW, and OBSOLETE.
What a buyer actually does at each stage:
- ACTIVE — nothing. Re-check at each BOM review.
- NRND — start qualifying an alternate now. You have time; you do not have forever.
- LIFEBUY / last-time-buy — get the LTB date in writing, calculate remaining lifetime demand, and place the buy. This is the stage most programmes get wrong, because the LTB window closes while the alternate is still being qualified.
- OBSOLETE — you are in the open market. Traceability, inspection and test are now your problem, not the vendor’s.
The GAL22V10 is the textbook case, and it happens to be a DIP part. Lattice discontinued the GAL22V10D in June 2010, with last shipment in June 2011, and offered no pin-compatible replacement of its own. Microchip’s ATF22V10C family did — and still ships.
Table 6 — Alternates and cross-reference: GAL22V10D
| Alternate | Vendor | Grade | Package | Key difference | What you must re-verify | Lifecycle |
| ATF22V10C | Microchip | [PIN-COMPAT] | 24-lead 300-mil PDIP (24P3) | EE CMOS; faster grades available; optional pin-controlled power-down on pin 4 of the DIP/SOIC package | Speed grade, ICC, whether you use the PD pin (if you do, that pin is unavailable as a logic input), programmer support | Active |
| ATF22V10CQ / CQZ | Microchip | [PIN-COMPAT] | 24-lead 300-mil PDIP | Low-power / zero-power variants | Standby current, wake-up timing | Active |
| ATF22LV10C | Microchip | [FUNCTIONAL] | 24-lead 300-mil PDIP | 3.3 V rail | Supply rail and I/O levels across the whole board — this is a redesign, not a swap | Active |
| ATF22V10C-15GM/883 | Microchip | [MIGRATION] | 24-lead 300-mil CERDIP (24D3) | Military, −55 °C to +125 °C, MIL-STD-883 Class B; DSCC SMD 5962-8984115LA | Screening flow, price, lead time, export control | Active |
| GAL22V10D | Lattice | — | 24-lead DIP | The original | — | Discontinued (last shipment June 2011) |
Source: Microchip ATF22V10C datasheet (doc0735); Microchip knowledge base (GAL22V10 replacement guidance); Lattice GAL22V10 discontinuation record.
Why we don’t say “drop-in”. Microchip’s knowledge base states that the ATF22V10C/CQ/CQZ are pin-to-pin and JEDEC-fusemap compatible with the GAL22V10 — which is why we grade them [PIN-COMPAT] and not [DROP-IN]. Timing, supply current and the power-down pin behaviour are not identical to the Lattice original. Re-verify against your timing budget before you cut a purchase order. Vendors and brokers who call this a drop-in are guessing on your behalf.
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How to check a DIP part isn’t counterfeit
DIP is the most-faked package format on the open market, and the reason is structural: the parts are old, the demand is legacy and retro, the volumes are small, and the flat plastic top is trivial to sand and re-mark.
The mechanism is almost always the same. Take a cheaper, dead or recycled die. Sand the top of the package. Apply a coating — “blacktop”. Print new markings. Invent a date code.
The tells, in order of cost:
1. Markings. Genuine parts are laser-etched. Counterfeit markings are printed onto a coating. In a documented open-market case, a buyer received parts marked ATmega88PA-PU in DIP-28 whose top markings wiped off with acetone; genuine laser etching does not dissolve. Both samples carried the same date code — 1910, week 10 of 2019 — which is itself a tell in a small open-market lot.
2. Surface and mould cavities. Sandblasting rounds corners and edges and leaves the pin-1 cavity and other mould cavities unclean or partially filled. Inspect at 30× with a camera on the microscope, because you will need to send the photographs to someone.
3. Solvent tests. AS6081 specifies a destructive escalation, in this order: acetone (swab the surface; if the swab blackens or the surface permanently changes colour, the part is coated and suspect), then 1-methyl-2-pyrrolidinone (immerse, 115–120 °C, 2–5 minutes), then Dynasolve 750, preheated. The ladder exists because counterfeiters moved to acetone-resistant blacktop, which is also why the scrape test was added. MIL-STD-883 Method 2015 defines the marking-permanence solvent — three parts mineral spirits to one part alcohol — that genuine marking is required to survive.
4. X-ray. Reveals an empty package with no die at all, a die that does not match the reference lead frame, or a recycled die with a new bond wire placed on top of an old ball bond.
5. Read the silicon ID — the DIP equivalent of a JTAG IDCODE check. You cannot JTAG a GAL. You can put it in a programmer. A TL866/minipro-class programmer will read the device signature and flag a mismatch against the declared part. In the ATmega case above, the part marked “88PA” returned signature 0x1E930A — an ATmega88A die. For a PLD, read the user electronic signature and the fuse map. This is the cheapest high-confidence test available on a DIP part, it takes ninety seconds, and almost nobody writes about it.
Table 7 — Counterfeit inspection ladder for DIP parts
| Step | Method | What it detects | Destructive | Reference |
| 1 | Visual, 30× microscope | Remarking, sanding, rounded edges, filled mould cavities, logo and font errors, crooked marking | No | IDEA-STD-1010 |
| 2 | Date- and lot-code audit | A single date code across a supposedly mixed lot; a date code newer than the die revision | No | AS6081 (traceability) |
| 3 | Acetone swab | Blacktop / resurfacing | Semi | AS6081 |
| 4 | Scrape test | Acetone-resistant blacktop | Semi | Post-acetone industry practice |
| 5 | 1-methyl-2-pyrrolidinone, 115–120 °C, 2–5 min | Coating that survives acetone | Yes | AS6081 |
| 6 | Dynasolve 750, preheated | Coating that survives both | Yes | AS6081 |
| 7 | Device signature / fuse-map read on a programmer | Wrong die, dead die, cloned part | No | Vendor programming specification |
| 8 | X-ray | No die; wrong lead frame; recycled die (new bond wire on old ball) | No | AS6171 |
| 9 | XRF | Lead-finish and RoHS misdeclaration | No | AS6171 |
| 10 | Decapsulation and functional test | Everything else | Yes | AS6171 |
Source: SAE AS6081 (solvent test sequence); SAE AS6171 (test methods); IDEA-STD-1010-C (visual inspection); MIL-STD-883 Method 2015 (marking permanency).
Which counterfeit-avoidance standard applies to whom
| Standard | Applies to |
| AS5553 | OEMs and users of electronic parts |
| AS6081 | Independent distributors and brokers buying on the open market |
| AS6496 | Authorized / franchised distributors |
| AS6171 | Test laboratories — test methods |
| IDEA-STD-1010 | Visual and mechanical inspection at the bench |
| ERAI | Industry reporting database for suspect and confirmed counterfeit parts |
| DFARS 252.246-7007 | Flows AS5553 / AS6081 down to US DoD prime contractors |
Source: SAE International standards catalogue; DLA Land and Maritime counterfeit-standards briefing; DFARS 252.246-7007.
Sourcing desk: The single most useful thing you can ask an open-market supplier for on a DIP part is not a certificate. It is a photograph of the actual lot — top marking, date code, lot code, and the pin-1 cavity, at magnification. If they cannot produce that within the hour, the parts are not in their hands.
Five mistakes engineers make with DIP packages
- Assuming 24 pins means 600 mil. It often doesn’t. The ATF22V10C-15PU is a 24-lead part in a 300-mil body, and it is the part you will actually be shipped.
- Trusting the package abbreviation instead of the drawing. SDIP and SPDIP each carry two meanings, and one vendor uses both names for the same package in different documents.
- Printing an MSL row in the DIP spec table. J-STD-020 is scoped to surface-mount devices. The row is meaningless unless you are doing pin-in-paste.
- Using IPC-7351 land patterns. That is the surface-mount standard. Through-hole is IPC-7251, with hole and land sizes derived from IPC-2222 and IPC-2221.
- Assuming the DIP option will still exist next year. It is the first package a vendor drops. Check the lifecycle field before you commit the footprint, not after the PCN lands.
Frequently asked questions
Is DIP the same as PDIP?
Not quite. DIP is the format; PDIP is the plastic version of it. The other common variant is CDIP/CERDIP, a hermetic ceramic body used for military, high-temperature and UV-erasable EPROM parts. If a datasheet says “DIP” with no material letter, it almost always means plastic.
What is the difference between PDIP and SPDIP?
It depends on the vendor. In JEDEC and general industry usage, SPDIP means Shrink Plastic DIP, with a 1.778 mm lead pitch. Microchip uses SPDIP to mean Skinny Plastic DIP: normal 2.54 mm pitch in a narrow 300-mil body. Check the pitch on the package drawing, never the abbreviation.
What is the pin pitch and row spacing of a DIP package?
Lead pitch is 2.54 mm (0.100 in) on every standard DIP; Shrink DIP uses 1.778 mm. Row spacing varies: 7.62 mm (JEDEC MS-001), 10.16 mm (MS-010) and 15.24 mm (MS-011) are the registered outlines, with 22.86 mm on some large ceramic side-brazed parts.
How do I find pin 1 on a DIP package?
Hold the part with the notch or dimple at the top. Pin 1 is the top-left lead, and numbering runs counter-clockwise from there. Some parts also mark pin 1 with a printed dot. Where leads are physically missing, the remaining leads are still numbered as if all positions were populated.
Why are DIP packages limited to about 64 pins?
Because the leads must fan out radially from the die, in a single plane, to two rows on the package edge. More leads means a wider body and longer internal leads, which hurts both manufacturability and speed. The 64-lead DIP – the Motorola 68000, the Zilog Z180 – was the practical ceiling.
Is the DIP package obsolete?
No, but it is in managed decline. New silicon is rarely offered in DIP, and where it is, the DIP option is usually the first to be discontinued. Legacy logic, SPLDs, op-amps, 555 timers and 8-bit MCUs remain available. Treat every DIP line item on a BOM as a lifecycle risk.
Are DIP components still used in professional designs?
Yes – for legacy maintenance, for socketed or field-replaceable parts, for devices programmed off-board, and for anything that must be hand-assembled or repaired in the field. They are not used for new high-density or high-speed designs, where lead inductance and board area rule them out.
Can you get an FPGA in a DIP package?
No. No FPGA vendor – AMD/Xilinx, Altera, Lattice, Microchip, GOWIN or Efinix – offers a DIP option; current families are QFP, QFN, CSP and BGA. The workaround is a DIP-form-factor carrier module such as Digilent’s Cmod A7 (Artix-7) or Cmod S7 (Spartan-7), which brings FPGA I/O out on 100-mil through-hole pins.
What can I use instead of a discontinued GAL22V10?
Microchip’s ATF22V10C family. Lattice discontinued the GAL22V10D in June 2010, with last shipment in June 2011, and offered no pin-compatible replacement. Microchip states that the ATF22V10C/CQ/CQZ are pin-to-pin and JEDEC-fusemap compatible, and they remain in production in 24-lead 300-mil PDIP.
How do I tell if a DIP chip is counterfeit?
Start with the top marking: genuine parts are laser-etched, while fakes are usually printed onto a sanded-and-coated surface that acetone will lift. Then check date and lot codes, inspect the mould cavities at 30x, and read the device signature on a programmer. Escalate to X-ray if any of those fail.
Is IDEA-STD-1010 the same as AS6081?
No. IDEA-STD-1010 governs visual and mechanical inspection at the bench. AS6081 governs the entire quality system of an independent distributor buying on the open market. AS6496 covers authorized distribution and AS6171 covers test laboratories. Credible independents apply several of them together.
Does a DIP package have an MSL rating?
Generally no. J-STD-020, which defines moisture sensitivity levels, is scoped to non-hermetic surface-mount devices, because in through-hole assembly the board shields the package body from the molten solder. The exception is pin-in-paste (intrusive reflow), where a through-hole part passes through a reflow oven.
Sourcing a DIP part
The DIP package is not hard to understand. What is hard is buying one in 2026: the die is old, the vendor has moved on, the authorized stock is thin, and the open market is full of sanded plastic.
That is the part we do. Send us the part number and the quantity — an FPGA applications engineer reviews the request and comes back with price, lead time, lifecycle status and, where the original is gone, an honestly graded alternate.
