The PDIP package is a Plastic Dual In-line Package: a through-hole IC body with two parallel rows of pins on a 2.54 mm (0.1 in) pitch, spaced either 0.3 in or 0.6 in between rows, in counts from 8 to 64. It is the classic breadboard chip — the 555 timer, the 741 op-amp, and the DIP microcontroller all ship in one. Below are the full PDIP dimensions by JEDEC standard, the size for each pin count, and how the pinout numbering works.

Key takeaways

• PDIP pins sit on a 2.54 mm (0.1 in) grid, the defining pitch, with two rows spaced 0.3 in (7.62 mm) or 0.6 in (15.24 mm) apart (JEDEC MS-001 / MS-011).
• Three JEDEC families cover it: MS-001 (0.300 in rows, 6.35 mm body), MS-010 (0.400 in rows, 9.15 mm body), and MS-011 (0.600 in rows, 12.7 mm body).
• An 8-lead PDIP body is 9.02–9.27 mm long and 6.10–7.11 mm wide, with a maximum seated height of 5.33 mm (Analog Devices N-8, MS-001).
• Pin 1 is the upper-left pin when the notch or dot faces up; numbering runs counterclockwise down the left side and back up the right.
• Pin counts are always even (8, 14, 16, 20, 28, 40, …), split evenly between the two rows.
• PDIP is through-hole and not hermetic. For surface mount, its 1.27 mm-pitch cousin is SOIC; for a hermetic body, CDIP.

What the PDIP package is

PDIP stands for Plastic Dual In-line Package. It is a rectangular chip with leads down both long sides, bent to pass through holes in a board and solder on the far side. The die sits on a metal lead frame, wire-bonded to the leads, and the whole assembly is encapsulated in molded epoxy.

The plastic body is cheap and durable but not hermetic — epoxy is slightly porous, so a PDIP does not seal moisture out the way a ceramic package does. In a normal environment that is fine; PDIPs run reliably for decades. Where a hermetic seal or a UV-erase window is needed, the ceramic version (CDIP) is used instead.

PDIP has outlived most through-hole formats because it is easy to handle. A 2.54 mm pin grid solders by hand with a basic iron, drops into a breadboard, and fits a socket, which keeps the package alive for prototyping, education, and low-volume builds long after surface mount took over production.

[IMAGE 1: Dimensioned side and end view of an 8-lead PDIP showing pitch, row spacing, body length, and seated height | alt: “PDIP package dimensions 8-lead pitch row spacing body length”]

PDIP dimensions: the numbers that matter

Every PDIP shares the same 2.54 mm (0.1 in) pin pitch. What changes with the package is the row spacing — the distance between the two rows of pins — and the molded body width. JEDEC splits these into three plastic-DIP families.

JEDEC standard	Row spacing	Body width	Pin pitch	Typical counts
MS-001	0.300 in (7.62 mm)	6.35 mm (0.25 in)	2.54 mm (0.1 in)	8–28 (narrow)
MS-010	0.400 in (10.16 mm)	9.15 mm (0.36 in)	2.54 mm (0.1 in)	22–24
MS-011	0.600 in (15.24 mm)	12.7 mm (0.50 in)	2.54 mm (0.1 in)	24–48 (wide)

Row spacing is the number to match to your footprint: a 0.3 in part and a 0.6 in part of the same pin count are not interchangeable on the board. The 0.300 in (MS-001) family covers most 8- to 28-pin logic and analog parts; the 0.600 in (MS-011) family covers wider 24- to 48-pin devices like microcontrollers and older DRAM.

8-lead PDIP dimensions in full

The 8-lead PDIP is the canonical case — the body of the 555, the 741, and countless others. These are the controlled dimensions from an Analog Devices N-8 outline, compliant with JEDEC MS-001.

Dimension	Inches (min–max)	Millimeters
Lead pitch (e)	0.100 BSC	2.54 BSC
Row spacing (base)	0.300	7.62
Body length (D)	0.355–0.365	9.02–9.27
Body width (E1)	0.240–0.280	6.10–7.11
Overall height (A), max	0.210	5.33
Base standoff (A1), min	0.015	0.38
Lead thickness (c)	0.008–0.014	0.20–0.36
Lead width (b)	0.014–0.022	0.36–0.56
Lead width at body (b1)	0.045–0.070	1.14–1.78
Lead-tip span	0.300–0.325	7.62–8.26

Two notes for layout. The controlling dimensions are in inches; the millimeter values are rounded references, so build the footprint from the inch grid. And the leads splay outward from the body, so the tip-to-tip span (up to 8.26 mm) is wider than the 7.62 mm nominal row spacing — the reason a DIP grips a socket.

PDIP by pin count

Pin count sets the body length, since each added pair of pins adds one 2.54 mm pitch step. The row-spacing family and JEDEC standard follow the count.

Pins	Pins per row	Row spacing	JEDEC standard
8	4	0.3 in	MS-001
14	7	0.3 in	MS-001
16	8	0.3 in	MS-001
18	9	0.3 in	MS-001
20	10	0.3 in	MS-001
24	12	0.3 or 0.6 in	MS-001 / MS-011
28	14	0.3 or 0.6 in	MS-001 / MS-011
40	20	0.6 in	MS-011
48	24	0.6 in	MS-011
64	32	0.75 in (shrink)	SPDIP

Body length scales with the count: the 8-lead body is about 9.27 mm, and it grows by roughly 2.54 mm for every two pins added. Some counts exist in both widths — a 24- or 28-pin device may be a narrow 0.3 in “skinny DIP” or a wide 0.6 in part — so confirm the row spacing from the specific datasheet before laying out the footprint.

PDIP pinout and pin numbering

DIP numbering is fixed and worth committing to memory. Hold the package with the notch (a semicircular indent on one short end) or the pin-1 dot facing up. Pin 1 is the top-left pin. Numbers increase going down the left side, cross to the bottom-right pin, and increase going up the right side.

[IMAGE 2: Top view of a 14-lead PDIP showing the notch, pin-1 dot, and counterclockwise numbering | alt: “PDIP pinout pin 1 notch counterclockwise numbering 14-lead”]

So on a 14-pin DIP, pin 1 is top-left and pin 14 is top-right; pin 7 is bottom-left and pin 8 is bottom-right. Getting this wrong is the classic first-build error — a chip inserted 180° out puts power and ground on the wrong pins and usually destroys the part. Match the package notch to the notch printed on the silkscreen or socket.

PDIP vs CDIP, SOIC, and SPDIP

PDIP is one point in the DIP family. The table compares it with the ceramic version, the surface-mount equivalent, and the shrink variant.

Package	Pin pitch	Mounting	Body	Hermetic?	Notes
PDIP	2.54 mm (0.1 in)	through-hole	epoxy plastic	no	cheapest, breadboard/socket-friendly
CDIP	2.54 mm (0.1 in)	through-hole	ceramic	yes	windowed for EPROM; high-temp (MS-015)
SPDIP	1.778 mm (0.07 in)	through-hole	epoxy plastic	no	denser shrink variant
SOIC	1.27 mm (0.05 in)	surface-mount	epoxy plastic	no	SMD equivalent (MS-012/013)

The decision is usually PDIP versus SOIC. SOIC keeps the dual-row layout but halves the pitch to 1.27 mm and solders to the surface, saving board area and enabling automated assembly, at the cost of hand-soldering ease. Choose PDIP when you need to socket, breadboard, or hand-build; choose SOIC or smaller for production density. SPDIP splits the difference for through-hole, tightening the pitch to 1.778 mm.

Footprint, soldering, and design notes

A PDIP footprint is a double row of plated through-holes on a 2.54 mm grid, with the rows 0.3 in or 0.6 in apart. A finished hole around 0.8–1.0 mm clears the lead, which measures roughly 0.36–0.56 mm wide and 0.20–0.36 mm thick on an 8-lead part (Analog Devices N-8). Confirm the hole against the lead dimensions in the datasheet.

PDIPs are wave-soldered or hand-soldered, not reflowed, because the leads go through the board. Modern parts use lead-free (RoHS) plating — tin over copper alloy is typical — so match your solder and profile accordingly. For anything that will be inserted and removed, use a socket rather than soldering the chip, and orient pin 1 before insertion.

Availability is the other design factor. Many jellybean parts remain in PDIP, but newer devices increasingly skip it. If a design depends on a socketed DIP, check that the exact part is still stocked in the package before committing, since PDIP is often the first option a manufacturer drops.

Frequently asked questions

What does PDIP stand for?

PDIP stands for Plastic Dual In-line Package. It is a through-hole IC package with two parallel rows of pins on a 2.54 mm (0.1 in) pitch, encapsulated in molded epoxy plastic. Pin counts run from 8 to 64, and the rows are spaced 0.3 in or 0.6 in apart.

What is the pin pitch and row spacing of a PDIP?

PDIP pins are on a 2.54 mm (0.1 in) pitch. The two rows are spaced 0.3 in (7.62 mm) apart on narrow MS-001 parts or 0.6 in (15.24 mm) on wide MS-011 parts, with 0.4 in (10.16 mm) MS-010 and 0.9 in variants less common. Pitch is fixed; row spacing depends on the part.

How do you number PDIP pins?

Hold the package with the notch or pin-1 dot up. Pin 1 is the top-left pin. Numbering runs counterclockwise: down the left side, across to the bottom-right, and up the right side. On a 14-pin DIP, pin 1 is top-left, pin 7 bottom-left, pin 8 bottom-right, and pin 14 top-right.

What is the difference between PDIP and DIP?

DIP (dual in-line package) is the general format; PDIP is the plastic-bodied version. The main alternatives are CDIP (ceramic, hermetic, often windowed for EPROMs) and SPDIP (shrink plastic, 1.778 mm pitch). In casual use, “DIP” usually means a PDIP.

Is PDIP the same as DIP-8 or DIP-40?

“DIP-8” and “DIP-40” name the pin count, not the material — most are PDIPs. A DIP-8 is an 8-lead package (four pins per row, 0.3 in spacing); a DIP-40 is 40-lead (20 per row, 0.6 in spacing, JEDEC MS-011). Both are usually plastic unless marked ceramic.

Is PDIP still used?

Yes, but mostly for prototyping, education, and low-volume or serviceable designs. Surface-mount packages dominate production, and many new parts skip PDIP entirely. Jellybean logic, timers, op-amps, and some microcontrollers remain available in PDIP; verify stock for the exact part before designing it in.

Bottom line

Reach for PDIP when you need a chip you can socket, breadboard, or hand-solder, and reach for the datasheet for the one dimension that varies — the row spacing, 0.3 in or 0.6 in, since pitch is always 2.54 mm. Build the footprint from the inch grid, size the holes to the lead, and set pin 1 by the notch before you insert. For production density, move to SOIC or smaller; for a hermetic or windowed part, move to CDIP. Otherwise the plastic DIP remains the simplest package to work with by hand.

[IMAGE 3: Size comparison of an 8-lead PDIP beside an 8-lead SOIC at the same scale | alt: “PDIP versus SOIC size comparison 8-lead through-hole surface mount”]

External primary sources

• Analog Devices — 8-Lead PDIP Narrow Body (N-8), JEDEC MS-001: https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/pdipn/n_8.pdf
• JEDEC Publication 95 — Master Index (MS-001 / MS-010 / MS-011): https://www.jedec.org/sites/default/files/Master.pdf
• JEDEC — Microelectronic Standards (MS) Index: https://www.jedec.org/sites/default/files/MSINDEX_0.pdf
• Texas Instruments — Dual In-Line (DIP) package search: https://www.ti.com/packaging/docs/searchtipackages.tsp?packageName=DIP