A JEDEC package outline is a registered mechanical drawing that fixes a package’s exact dimensions and tolerances, and it is the real definition of whether two parts share a footprint. The designations come in two forms: MO for registered outlines and MS for standard outlines, both catalogued in JEDEC publication JEP95. This guide explains the difference, decodes the variation letter that sets pin count, and walks you through reading an actual drawing — dimension letters, BSC, and all.
[IMAGE 1: an annotated SOIC outline drawing with dimension letters A, A1, b, D, E, E1, e, L, and theta called out on top, side, and end views | alt: “How to read a JEDEC package outline: annotated SOIC drawing showing dimension letters A, A1, b, D, E, e, and lead angle”]
Key takeaways
- JEP95 holds over 500 outlines, including 363 MO (registered) and 34 MS (standard) drawings, plus 55 TO and 42 CO, per JEDEC’s catalog.
- MO vs MS is procedural, not quality: MO outlines are registered by a member company; MS outlines are prepared by the JC-11 committee for widely multi-sourced packages.
- The variation letter sets the size: MS-012-AA is an 8-lead SOIC, MS-012-AB is 14-lead, MS-012-AC is 16-lead — same family, different pin count.
- BSC means basic — a theoretically exact dimension with no ± tolerance; REF (or a value in parentheses) is a reference dimension that is not inspected.
- The drawing gives the component body; the PCB land pattern comes from IPC-7351, not from soldering to the JEDEC dimensions directly.
What a JEDEC package outline is
A JEDEC package outline is a standardized mechanical drawing, held in JEP95, that specifies a package’s body size, lead dimensions, pitch, and tolerances. The JEDEC JC-11 committee on mechanical standardization develops and maintains these outlines. When a datasheet says a part is “compliant to JEDEC MS-012-AC,” it is claiming the part matches that registered geometry, which is what lets a footprint from one vendor fit a part from another.
This matters because a marketing name like “SOIC-16” is not precise enough to guarantee interchangeability. The JEDEC outline is. Two SOIC-16 parts that both cite MS-012-AC will drop onto the same land pattern; two that cite different outlines may not.
MO vs MS: registered versus standard outlines
The prefix tells you how the drawing entered the registry, and it is a common source of confusion. Per Texas Instruments’ JEP95 application report SZZA006, a registered outline (MO-nnn) is submitted by a member company and then standardized by JC-11; the MO number sits near the lower-right corner of the drawing. A standard outline (MS-nnn) is prepared by the committee itself for a package in broad, multi-source use, and carries a JEDEC Council approval statement on page one.
Neither is “better.” MO simply means a company originated the geometry; MS means the committee standardized a widely-used package from the start. Both are equally valid references, and a package family can hold both forms over time.
The registry uses other prefixes too. TO covers transistor outlines (TO-3, and SOT-23 is registered as TO-236), DO covers diodes (DO-41), and CO covers carrier outlines like shipping tubes and trays, per JEDEC. By JEDEC’s own catalog, there are roughly 363 MO, 34 MS, 55 TO, and 42 CO entries — so registered microelectronic outlines vastly outnumber the committee-standard ones.
Decoding the designation and its variation letter
A full designation has three parts: the prefix (MO or MS), the family number, and a two-letter variation code. The variation letter is what sets the pin count and body length within a family.
| Designation | Package | Leads |
| MS-012-AA | SOIC narrow | 8 |
| MS-012-AB | SOIC narrow | 14 |
| MS-012-AC | SOIC narrow | 16 |
| MS-013-AA | SOIC wide | 16 |
| MS-018-AA | PLCC | 28 |
| MS-018-AB | PLCC | 32 |
Monolithic Power’s SOIC-8 drawing states it “conforms to JEDEC MS-012, variation AA,” and Analog Devices’ 16-lead narrow SOIC drawing states compliance to “MS-012-AC,” per their package documents. So when you see MS-012-AC on a datasheet, you already know it is a 16-lead narrow-body SOIC before you read a single dimension. The datasheet’s package drawing is always the authority for the exact numbers.
Reading the drawing: the dimension letters
JEDEC outlines use a consistent set of letter symbols, mirrored on manufacturer drawings. Learn these once and every outline becomes readable.
| Symbol | Dimension |
| A | Overall height (top to seating plane) |
| A1 | Standoff (seating plane to package bottom) |
| A2 | Body thickness |
| b | Lead width |
| c | Lead thickness |
| D | Body length |
| E | Overall width including leads (lead span) |
| E1 | Body width |
| e | Lead pitch |
| L | Foot length (the part that solders to the pad) |
| θ | Lead foot angle |
| n | Number of leads |
A drawing shows top, side, and end views, all referenced to the seating plane — the datum the package rests on, from which A and A1 are measured. Note that letter usage varies slightly between vendors: some use D and E for the body and add HD and HE for the span, so confirm the legend on each drawing. Microchip’s TO-92 drawing, for instance, labels overall length D, overall width E1, and lead width B, and cites JEDEC equivalent MO-087, per its packaging specification.
[IMAGE 2: a MS-012-AC designation broken into prefix (MS = standard), family (012 = SOIC narrow), and variation (AC = 16-lead) | alt: “JEDEC designation decoded: MS-012-AC means standard outline, SOIC narrow family, 16-lead variation”]
BSC, REF, tolerances, and GD&T
Two abbreviations trip up first-time readers. BSC stands for basic spacing between centers — a basic dimension that is theoretically exact and carries no ± tolerance. Pitch is almost always given as a BSC value, such as e = 1.27 BSC; the allowable variation is captured by a true-position tolerance, not by a range on the BSC number itself.
REF marks a reference dimension, provided for information and not subject to inspection. Per ASME Y14.5-2009 section 1.7.6, the modern convention encloses reference dimensions in parentheses, so a value like (0.475) means the same thing as the older “0.475 REF.”
Most other dimensions appear as a MIN / NOM / MAX triple, often in millimeters with inches in brackets or vice versa; the drawing marks which unit is the controlling dimension. JEDEC outlines are dimensioned per ASME Y14.5, the GD&T standard, which is why you also see coplanarity — the requirement that all lead tips lie in one plane. A typical narrow SOIC specifies lead coplanarity of 0.10 mm (0.004 in) maximum, per Monolithic Power and Analog Devices drawings; exceed it and the part will not seat flat for reflow.
Worked example: reading a SOIC-16 (MS-012-AC)
Take Analog Devices’ 16-lead narrow-body SOIC, drawing R-16-S, compliant to MS-012-AC. Reading its dimension table gives a complete picture in millimeters.
| Symbol | Dimension (mm) |
| D (body length) | 9.80 / 9.90 / 10.00 |
| E1 (body width) | 3.80 / 3.90 / 4.00 |
| E (lead span) | 5.80 / 6.00 / 6.20 |
| e (pitch) | 1.27 BSC |
| A (height) | 1.35 / 1.55 / 1.75 max |
| A1 (standoff) | 0.10 / 0.18 / 0.25 |
| b (lead width) | 0.31 / 0.41 / 0.51 |
| θ (lead angle) | 0° to 8° |
| Coplanarity | 0.10 |
Read it top to bottom: the body is nominally 9.90 × 3.90 mm, the leads span 6.00 mm tip to tip, the pitch is exactly 1.27 mm, the part stands at most 1.75 mm tall, and every lead tip must sit within 0.10 mm of the seating plane, per the ADI drawing. That is enough to confirm the part against a datasheet and to derive its land pattern. Notice the lead span (E) is what your pads straddle, while the body width (E1) is what sits between them — mixing the two is a classic footprint error.
Common packages and their JEDEC outlines
| Package | JEDEC outline | Note |
| PDIP (0.3″ row) | MS-001 | 2.54 mm pitch |
| SOIC narrow | MS-012 | AA/AB/AC = 8/14/16 |
| SOIC wide | MS-013 | 7.5 mm body |
| TSSOP | MO-153 | 0.65 mm pitch |
| TSSOP, exposed pad | MO-194 | 0.4 mm pitch |
| QFP | MO-086 | four-side leads |
| TQFP / LQFP | MS-026 | 1.4 mm high (LQFP) |
| QFN | MO-220 | no-lead |
| PLCC | MO-047 / MS-018 | J-lead |
| SOT-23 | TO-236 | small-signal |
| TO-92 | MO-087 | through-hole transistor |
From outline to footprint (IPC-7351)
A JEDEC outline defines the component, not the copper. You do not solder to the outline dimensions; you solder to a land pattern, and the industry method for deriving that pattern is IPC-7351. It takes the JEDEC body and lead geometry, adds solder fillet targets and placement tolerance, and produces pad sizes and spacing.
The two work together. The JEDEC outline tells you the part’s true size and lets you confirm interchangeability; IPC-7351 turns that size into pads. Skipping IPC-7351 and drawing pads straight from the body dimensions is how boards end up with poor fillets and tombstoned parts. Always derive the footprint, then verify pad geometry against the specific datasheet.
JEDEC vs JEITA vs IEC
JEDEC is not the only body that registers package outlines, and the systems do not use the same symbols. Per TI’s SZZA006, JEDEC, JEITA (formerly EIAJ), and IEC each use different symbology and formats, which makes moving a registration between them cumbersome.
The practical consequence shows up in SOIC. The JEDEC MS-012 narrow body is 3.9 mm wide, while the JEITA/EIAJ Type II SOIC is 5.3 mm wide and slightly longer, per package references. Both get sold as “SOIC,” so the name alone does not tell you which body you are getting. Check the JEDEC or JEITA outline cited on the datasheet before you assume two SOIC parts share a footprint.
Mistakes when reading outlines
- Ignoring the variation letter. MS-012 alone is a family; only the AA/AB/AC suffix pins the pin count and length. Read the full designation.
- Confusing lead span (E) with body width (E1). Your pads straddle E; E1 sits between them. Swapping them breaks the footprint.
- Treating BSC as a toleranced value. BSC is exact; the tolerance lives in the position callout, not a ± on the pitch.
- Soldering to the body dimensions. Derive the land pattern from IPC-7351, not from the JEDEC outline directly.
- Missing the controlling unit. A drawing controls in either millimeters or inches; reading the converted value as the master introduces rounding error.
- Overlooking coplanarity and max height. A part can meet every planar dimension and still fail to seat if coplanarity is out, or fail to fit under a shield if A exceeds your budget.
FAQ
What is a JEDEC package outline?
A JEDEC package outline is a registered mechanical drawing, catalogued in JEP95 and maintained by the JC-11 committee, that fixes a package’s body size, lead dimensions, pitch, and tolerances. Designations are MO for registered outlines and MS for standard outlines. A datasheet citing one claims the part matches that exact geometry.
What is the difference between MO and MS in JEDEC?
The difference is procedural. An MO (registered outline) is submitted by a member company and then standardized by the JC-11 committee. An MS (standard outline) is prepared by the committee itself for a widely multi-sourced package. Neither is higher quality; both are valid references in JEP95, and registered MO outlines far outnumber MS ones.
What does BSC mean on a package drawing?
BSC stands for basic spacing between centers — a basic, theoretically exact dimension that carries no plus-or-minus tolerance. Lead pitch is almost always a BSC value, like 1.27 BSC. The allowable variation is controlled by a true-position tolerance elsewhere on the drawing, not by a range on the BSC number.
What does the variation letter like AA or AB mean?
The two-letter variation code sets the size within a package family, usually the pin count and body length. For the narrow SOIC family MS-012, variation AA is 8-lead, AB is 14-lead, and AC is 16-lead. So MS-012-AC tells you it is a 16-lead narrow SOIC before you read any dimensions.
What is the difference between JEDEC and JEITA packages?
JEDEC and JEITA (formerly EIAJ) are separate standards bodies that register package outlines with different symbols and, sometimes, different sizes. The clearest example is SOIC: the JEDEC MS-012 body is 3.9 mm wide, while the JEITA Type II body is 5.3 mm. Both are sold as SOIC, so check the cited outline.
How do I turn a JEDEC outline into a PCB footprint?
Do not use the outline dimensions as pads. Feed the JEDEC body and lead geometry into IPC-7351, which adds solder-fillet targets and placement tolerance to produce pad sizes and spacing. Then verify the resulting land pattern against the specific part’s datasheet, since manufacturers vary within an outline.
The bottom line
Read a JEDEC outline in this order. Decode the designation first — MO or MS, the family number, and the variation letter that sets pin count. Then read the drawing: the seating plane as your datum, the letter symbols for each dimension, and the MIN/NOM/MAX or BSC value for each. Remember that BSC is exact, REF is not inspected, and the drawing gives the body, not the pads. When you need a footprint, run the geometry through IPC-7351 and confirm it against the datasheet — and when you second-source, match on the full outline designation, because the family name alone does not guarantee a fit.
Internal links: IC package naming conventions decoded · electronic component packages (types overview) · IPC-7351 land patterns · inductor package sizes and case codes · hermetic packages (ceramic/metal-can).
External primary sources: JEDEC JEP95 registered outlines and standards catalog (jedec.org); TI application report SZZA006 (ti.com); Analog Devices SOIC-16 outline R-16-S (analog.com); Microchip Packaging Specification DS00049 (microchip.com); ASME Y14.5 GD&T standard (asme.org).
