The TO-268, commonly called D3PAK (Decawatt 3 Package), is the largest surface-mount package in the JEDEC DPAK family. Sitting above the TO-252 (DPAK) and TO-263 (D2PAK) in thermal capacity, the TO-268 (D3PAK) package provides an exposed-pad area of approximately 105 mm², roughly double that of the D2PAK. It houses high-voltage SiC MOSFETs, silicon IGBTs, and power diodes from Microchip (formerly Microsemi) and other vendors. This reference consolidates the verified package dimensions, a recommended land pattern, thermal data, and a head-to-head comparison with the rest of the DPAK family.

Key Takeaways

• The TO-268AA (3-lead) body measures approximately 15.9 mm wide × 10.0 mm long × 4.5 mm tall, with a 5.08 mm lead pitch.

• Exposed-pad area is roughly 105 mm², nearly double the D2PAK’s ~55 mm².

• Typical RθJC ranges from 0.3 to 1.0 °C/W; RθJA on a 4-layer JEDEC board is approximately 25–35 °C/W.

• Only the 3-pin variant (TO-268-3 / TO-268AA) is widely produced. Unlike D2PAK, no 5- or 7-pin variants exist in common use.

• Primary vendor: Microchip Technology (formerly Microsemi) for SiC MOSFETs (e.g., MSC750SMA170S at 1700 V, 750 mΩ; MSC017SMA120S at 1200 V, 17 mΩ).

What Is the TO-268 (D3PAK) Package?

The TO-268 (D3PAK) is a JEDEC-registered surface-mount power package with gull-wing leads and a large exposed thermal pad on its underside. D3PAK stands for Decawatt 3 Package, the third and largest member of the DPAK family after TO-252 (DPAK) and TO-263 (D2PAK). It is used almost exclusively for high-power discrete devices: SiC MOSFETs, silicon power MOSFETs, IGBTs, and fast-recovery diodes. The JEDEC designation is TO-268AA for the 3-lead variant. The package is also known as R-PSFM-G2 in the JEDEC Publication 95 index.

[IMAGE 1: Annotated TO-268 D3PAK package outline drawing | alt: “TO-268 D3PAK package outline dimensions”]

TO-268 Package Outline Dimensions

The table below compiles dimensions from the Microchip MSC750SMA170S and MSC360SMA120S datasheets (package drawing for D3PAK/TO-268), cross-referenced with the eesemi.com and madpcb.com D3PAK specifications.

Parameter	Symbol	Min (mm)	Typ (mm)	Max (mm)
Body width	E	15.50	15.90	16.26
Body length (leads to tab)	D	9.50	10.00	10.41
Overall height	A	4.19	4.50	4.70
Standoff	A1	0.00	—	0.30
Lead width	b	0.89	—	1.40
Lead thickness	c	0.46	—	0.74
Lead pitch	e	—	5.08 BSC	—
Lead foot length	L	3.81	—	3.96
Overall lead span	H	18.29	—	20.07
Exposed-pad width	E1	12.70	—	13.46
Exposed-pad length	D1	7.37	—	8.38
Mold flash (per side)	—	—	—	0.127

Sources: Microchip MSC750SMA170S datasheet (D3PAK package drawing); Microchip MSC360SMA120S datasheet; eesemi.com D3PAK reference; madpcb.com D3PAK glossary.

The lead pitch of 5.08 mm (200 mils) matches the TO-247 through-hole package and is wider than the D2PAK’s 2.54 mm. The terminal length of 150–156 mils (3.81–3.96 mm) is similar to D2PAK leads. Controlling dimension is millimeters per ASME Y14.5M.

DPAK Family Comparison: DPAK vs D2PAK vs D3PAK

The three DPAK-family packages share the same gull-wing SMD form factor but scale upward in thermal pad area, die capacity, and board footprint. The table below compares the key parameters.

Parameter	TO-252 (DPAK)	TO-263 (D2PAK)	TO-268 (D3PAK)
JEDEC designation	TO-252AA	TO-263AB	TO-268AA
Body width (mm)	≈6.5	≈10.0	≈15.9
Body length (mm)	≈6.1	≈9.0	≈10.0
Height (mm)	≈2.3	≈4.6	≈4.5
Lead pitch (mm)	2.29	2.54	5.08
Pin variants	3, 5	3, 5, 7	3 only
Exposed-pad area (mm²)	≈30	≈55	≈105
RθJC, typical (°C/W)	1.5–3.0	0.5–2.2	0.3–1.0
RθJA, 4-layer (°C/W)	50–60	25–40	25–35
Typical PD, PCB mount (W)	1.0–1.5	2.0–3.8	5–10
SMD heatsink weight (g)	2.3	3.1	3.7
Package weight (g)	≈0.5	≈1.4	≈2.0

Sources: Aavid Thermalloy 573300 datasheet (heatsink weights); prior fpga.io TO-263 article (D2PAK data); Microchip MSC datasheets (D3PAK thermal data); mbedded.ninja (DPAK data).

[IMAGE 2: Side-by-side photos of DPAK, D2PAK, and D3PAK at the same scale | alt: “DPAK vs D2PAK vs D3PAK surface-mount power package comparison”]

Recommended Land Pattern and Stencil

The recommended IPC-7351 Nominal land pattern for the TO-268AA uses the following pad geometry. All coordinates referenced from the component centroid.

Pad	Width (mm)	Length (mm)	Center X (mm)	Center Y (mm)
Pin 1	1.5	2.5	−5.08	−7.5
Pin 3	1.5	2.5	+5.08	−7.5
Thermal pad	15.0	9.0	0.00	+1.5

Courtyard: approximately 22 mm × 16 mm (0.5 mm clearance beyond pads). The footprint in mbedded.ninja’s library and Microchip’s recommended land pattern documents are broadly consistent with these values.

Stencil: Segment the thermal-pad aperture into a 5 × 4 grid with 0.3–0.5 mm webs, targeting 50–60% paste coverage. This limits solder voiding under the large pad to below 25%, consistent with IPC Class 2 assembly requirements.

Thermal vias: Use 0.3 mm drill vias on 1.2–1.5 mm pitch in a 5 × 4 array (20 vias). Tent or plug the via barrels on the solder side to prevent wicking. Each via contributes approximately 70–100 °C/W; the full array reduces the via thermal resistance contribution below 5 °C/W.

[IMAGE 3: TO-268 D3PAK land pattern with thermal via array and stencil grid | alt: “TO-268 D3PAK PCB land pattern with thermal vias and stencil aperture grid”]

Thermal Design Considerations

The D3PAK’s exposed-pad area (≈105 mm²) is its defining advantage. It accepts die sizes roughly double what fits in a D2PAK, enabling SiC MOSFETs with 17 mΩ RDS(on) at 1200 V (Microchip MSC017SMA120S) — a resistance level that would require paralleling two D2PAK devices.

Junction-to-case thermal resistance varies by device. The MSC750SMA170S (1700 V SiC MOSFET) specifies RθJC = 0.60 °C/W. The MSC090SMA070S (700 V, 90 mΩ SiC MOSFET in D3PAK) specifies RθJC = 0.45 °C/W per its datasheet. For comparison, typical D2PAK MOSFETs sit at 0.5–2.2 °C/W.

RθJA on a standard JEDEC 4-layer board with 1 in² of copper connected to the thermal pad is approximately 25–35 °C/W, improving to below 20 °C/W with a clip-on SMD heatsink such as the Aavid Thermalloy 573300D00010G (18 °C/W, copper, tin-plated, 12.7 mm × 26.16 mm × 10.16 mm, 3.7 g).

Common Devices in the TO-268 (D3PAK)

The D3PAK is predominantly a Microchip Technology (formerly Microsemi) package, though a handful of IGBTs from other vendors also appear in it.

SiC MOSFETs: Microchip MSC017SMA120S (1200 V, 17 mΩ at VGS = 20 V, D3PAK); MSC360SMA120S (1200 V, 360 mΩ); MSC750SMA170S (1700 V, 750 mΩ); MSC090SMA070S (700 V, 90 mΩ). These are all part of Microchip’s mSiC product line.

IGBTs: Microchip APT20GN60SDQ2G (600 V, 40 A, 136 W, Trench Field Stop IGBT in D3PAK).

Power MOSFETs: Microchip’s Power MOS 7 and Power MOS 8 families include D3PAK options. Part numbers use an “S” suffix to denote the D3PAK variant (e.g., replace “B” with “S” in the standard part number).

Power diodes: Fast-recovery and Schottky diodes from the Microsemi/Microchip portfolio are available in D3PAK for high-current rectification in switch-mode power supplies.

Soldering and Assembly

The D3PAK is compatible with standard SMT reflow processes. For SAC305 solder paste, follow a peak reflow temperature of 245 ± 5 °C with time above liquidus (TAL) of 60–90 seconds. The package’s mass (~2.0 g) can act as a heat soak during reflow; ensure your thermal profile accounts for this. Most D3PAK devices from Microchip classify as MSL 1 per J-STD-020, meaning unlimited floor life.

Hand soldering is feasible with a 60+ W iron. Tack the leads first, then flow solder onto the exposed tab using a broad chisel tip. Verify solder wetting across the full tab area under magnification. Incomplete tab solder coverage is the most common D3PAK assembly defect and directly degrades thermal performance.

Frequently Asked Questions

What is the difference between D2PAK and D3PAK?

D2PAK (TO-263) and D3PAK (TO-268) are both surface-mount power packages with exposed thermal pads. The D3PAK is roughly 60% wider (15.9 mm vs 10.0 mm) and has double the exposed-pad area (~105 mm² vs ~55 mm²). The D3PAK uses a 5.08 mm lead pitch versus D2PAK’s 2.54 mm. D3PAK is primarily available in a 3-pin variant only.

What is D3PAK used for?

D3PAK houses high-power SiC MOSFETs, silicon IGBTs, power MOSFETs, and fast-recovery diodes from Microchip Technology (formerly Microsemi). Applications include high-voltage switch-mode power supplies, solar inverters, EV chargers, and motor drives where 5–10 W of surface-mount power dissipation is needed without a through-hole heatsink.

Is D3PAK footprint-compatible with D2PAK?

No. The D3PAK is significantly larger (15.9 mm vs 10.0 mm body width) and uses a different lead pitch (5.08 mm vs 2.54 mm). It requires its own dedicated PCB footprint. A D2PAK device cannot be placed on a D3PAK pad and vice versa.

How much power can a D3PAK dissipate?

Board-dependent. On a bare PCB with minimal copper, 5–10 W is typical at TA = 25 °C. With a proper 4-layer stackup, generous copper fills, a thermal-via array, and a clip-on SMD heatsink, practical dissipation can reach 15–20 W. The datasheet PD rating at TC = 25 °C (often 100–300 W for SiC MOSFETs) assumes an infinite heatsink.

Who makes devices in D3PAK?

Microchip Technology (via its Microsemi acquisition) is the dominant supplier, particularly for SiC MOSFETs. DigiKey lists TO-268-3 / D3PAK MOSFETs and IGBTs almost exclusively from Microchip. The package is not widely adopted by other major vendors (Infineon, onsemi, STMicroelectronics), who favor TO-247, TO-247PLUS, or power modules for similar power levels.

When to Choose the D3PAK

Specify the D3PAK when your design needs surface-mount assembly at power levels above what a D2PAK can handle (>3 W board-mount) and below what justifies a through-hole TO-247 or a power module. It is the standard package for Microchip’s mSiC SiC MOSFET line at 700–1700 V, where the larger die area delivers lower RDS(on) than any D2PAK alternative.

Stay with D2PAK when dissipation is below 3 W, board area is constrained, or you need multi-source availability from Infineon, onsemi, and STMicroelectronics. Move to TO-247 or TO-264 when you need through-hole mounting to an external heatsink. Move to a power module when current exceeds 40 A or when half-bridge integration simplifies your gate-drive layout.