The TO-18 package is a hermetic metal can measuring 4.52 to 4.95 mm across the cap, 4.32 to 5.33 mm tall, on a flange of 5.31 to 5.84 mm, with three leads on a 2.54 mm BSC pin circle. JEDEC renamed it TO-206AA. You pay several times the price of a plastic TO-92 for it, and none of that premium buys thermal performance. It buys a sealed cavity and access to MIL-PRF-19500 screening.

Key takeaways

• TO-18 is TO-206AA. TO-46, TO-52 and TO-72 are the same header with a different cap height or lead count.
• Two vendors publish 150 °C/W and 83.3 °C/W junction-to-case for the same 2N2222A in the same can. Read the datasheet you are actually buying against.
• The leads pass through glass seals. Bending them at the header vents the cavity, and the failure is invisible until the part corrodes.
• Junction-to-ambient sits near 300 to 325 °C/W. In free air this is a half-watt package regardless of what the case-referenced number says.
• No moisture sensitivity level applies. Hermetic through-hole parts fall outside J-STD-020, so there is no dry pack and no floor life.
• Screening drives cost more than silicon does. Commercial parts list near $1.12 at 1,000 pieces; a JANS device in the same can lists at $71.14.

[IMAGE 1: TO-18 metal can transistor beside a TO-92 for scale, index tab visible on the flange | alt: “TO-18 metal can transistor package showing the index tab and three leads”]

TO-18 dimensions from the case drawing

Two independent drawings for this outline agree to the hundredth of a millimetre, which is unusual and worth knowing. Both trace to the same registered military outline.

Feature	onsemi CASE 206AA Issue A	Central Semiconductor TO-18 R1
Flange diameter	5.31 to 5.84 mm	5.31 to 5.84 mm
Cap diameter	4.52 to 4.95 mm	4.52 to 4.95 mm
Overall height	4.32 to 5.33 mm	4.32 to 5.33 mm
Flange thickness	0.76 mm max	0.76 mm max
Lead diameter at the seal	0.41 to 0.48 mm	0.41 to 0.48 mm
Lead diameter below the gauge plane	0.41 to 0.53 mm	not dimensioned
Lead length	12.70 to 19.05 mm	12.70 mm min
Pin circle diameter	2.54 mm BSC	2.54 mm
Index tab width	0.91 to 1.17 mm	0.91 to 1.17 mm
Index tab angle from lead 1	45° BSC	not dimensioned
Device mass	not published	312.4 mg ±10%

The 45° index tab is the only orientation feature. It sits between two leads rather than in line with one, so a silkscreen mark that lines up with a pad is wrong by construction.

[IMAGE 2: annotated TO-18 outline, bottom view, showing the 2.54 mm pin circle and the 45 degree index tab | alt: “TO-18 package dimension drawing showing the 2.54 mm pin circle and 45 degree index tab”]

The TO-206 family, and why the old names persist

JEDEC folded every 2.54 mm pin circle header into TO-206. TO-18 became TO-206AA, TO-46 became TO-206AB, TO-52 became TO-206AC and TO-72 became TO-206AF. TO-206AD was added as a new three-lead outline with a 1.40 mm cap, and TO-206AE matches TO-18 but drops the minimum lead diameter requirement.

Cap height is the only thing separating the three-lead members. TO-18 stands 4.83 mm, TO-52 stands 3.30 mm and TO-46 stands 1.90 mm. TO-72 adds a fourth lead, usually bonded to the can so the case can be grounded for RF shielding, and TO-71 carries up to eight leads with a 45° minimum angle between neighbours.

Pin styles are not fixed by the outline

Central Semiconductor lists three lead codes against the same drawing. Transistors run emitter, base, collector. SCRs run cathode, gate, anode. Field effect transistors run source, gate, drain in one convention and source, drain, gate in another.

That second FET convention is the one that bites. Two JFETs in identical cans, from different vendors, can present drain and gate swapped. Confirm the lead code on the device datasheet before the footprint is released.

What the metal can actually buys: a sealed cavity

Central Semiconductor publishes the material breakdown for its TO-18 case. The header is Kovar, an iron nickel cobalt alloy, at 183.71 mg. The cap is a steel alloy at 114.99 mg with a nickel inner plating and a matte tin outer plating. The lead seals are glass at 42 mg. Total device mass is 312.4 mg.

Hermeticity is verified rather than assumed. MIL-STD-750 Test Method 1071 covers hermetic seal testing for discrete semiconductors, and JEDEC recommends the same method for commercial hermetic requirements. Both a fine leak and a gross leak test are run.

Allowable leak rate scales with cavity volume. NASA NEPP cites equivalent standard air leak rates under Method 1071 of 5 × 10⁻¹⁰ atm cc/s for cavities at or below 0.002 cc and 1 × 10⁻⁹ atm cc/s from there to 0.05 cc. A TO-18 cap encloses roughly 0.083 cm³ computed from the nominal 4.7 mm diameter and 4.8 mm height, and the free internal volume is smaller once header, die and wall thickness are subtracted. That places a TO-18 in the tightest brackets the standard defines.

One practical consequence: moisture sensitivity levels do not apply. J-STD-020 scopes itself to nonhermetic solid state surface mount devices. A hermetic through-hole can sits outside it, so there is no MSL rating, no dry pack and no floor life to track.

Thermal reality: a metal can is not a heat sink

The ratings below come from four datasheets for parts in the same outline. The spread is not a rounding difference.

Part and source	Type	V(BR)CEO	I C	P D at T A = 25 °C	P D at T C = 25 °C	Rθ JA	Rθ JC	T J max
2N2222A, onsemi Rev 2	NPN	50 V	800 mA	500 mW	1.0 W	325 °C/W	150 °C/W	200 °C
2N2222A, ST (obsolete)	NPN	40 V	600 mA	500 mW	1.8 W	300 °C/W	83.3 °C/W	175 °C
2N2907, Multicomp	PNP	40 V	600 mA	400 mW	1.8 W	derate 2.28 mW/°C	derate 10.3 mW/°C	200 °C
2N2222A, Central Semi	NPN	40 V	800 mA	500 mW	not listed	not listed	not listed	200 °C

The same registered part number carries a junction-to-case figure of 150 °C/W from onsemi and 83.3 °C/W from ST, with maximum junction temperatures of 200 °C and 175 °C respectively. Neither is wrong. They describe different die and different measurement references sold under one 2N number.

Junction-to-ambient tells the more useful story. At 300 to 325 °C/W, free-air dissipation is a few hundred milliwatts before the junction runs away. The case-referenced 1.0 W and 1.8 W numbers require a heat path to the flange that almost no TO-18 design actually provides.

Worked example: 300 mW at 70 °C ambient

Take a 2N2222A dissipating 300 mW in a 70 °C enclosure with no heatsinking.

Using the onsemi datasheet, junction temperature is 70 + (0.3 × 325) = 167.5 °C against a 200 °C limit, leaving 32.5 °C of margin. Using the ST datasheet, it is 70 + (0.3 × 300) = 160 °C against a 175 °C limit, leaving 15 °C. Same current, same package, half the margin.

If your derating policy caps the junction at 110 °C, as some avionics guidelines do, neither part passes at 300 mW. The allowable dissipation drops to about 123 mW on the onsemi numbers.

Mounting and handling: the leads are part of the seal

onsemi AN1040 is blunt about metal packages. Pins and lugs on devices using glass to metal seals are not designed to handle any significant bending or stress, and abusing them can crack the seals. The note also states that the leads of metal power packages are not designed to support the package, and that cases must be firmly supported to avoid cracked seals around the leads.

Read that against a 312.4 mg can held by three leads of 0.41 to 0.48 mm diameter. Under vibration the glass seals carry the load. That is why board-level support matters more here than on a plastic package of similar size.

Where you need controlled standoff, the hardware exists. Bivar lists the 105-021 circular component mount specifically for TO-18, in nylon, 6.35 mm outside diameter and 0.53 mm thick, carried by DigiKey as 492-1481-ND with 3,934 pieces in stock against a 12-week factory lead time.

AN1040 also recommends flexible or braided wire when connections are made directly to the pins, and permits sockets or crimp connectors. Wire wrapping is acceptable only if the lead is restrained between the case and the point of wrap.

[IMAGE 3: close view of a TO-18 header showing the glass to metal lead seals | alt: “TO-18 header glass to metal seals around the three transistor leads”]

PCB footprint on a 2.54 mm pin circle

Hole and pad sizing follows from the lead, not the can. Take the largest lead section, 0.53 mm below the gauge plane on the onsemi drawing.

IPC-2222 sets the minimum finished hole at maximum lead diameter plus 0.25 mm at Level A, 0.20 mm at Level B and 0.15 mm at Level C. Pad diameter is that hole plus twice the 0.05 mm annular ring plus the fabrication allowance, 0.6 mm at Level A and 0.5 mm at Level B.

Producibility level	Minimum finished hole	Pad diameter	Copper gap, leads 90° apart	Copper gap, leads 120° apart
Level A	0.78 mm	1.48 mm	0.32 mm	0.72 mm
Level B	0.73 mm	1.33 mm	0.47 mm	0.87 mm

The two clearance columns exist because the outline drawing fixes the pin circle diameter and the tab angle but leaves the angular lead positions to the device drawing. Chord length on a 2.54 mm circle is 1.796 mm for leads 90° apart and 2.199 mm for leads 120° apart. Either way Level B geometry clears comfortably, so the footprint is forgiving once the angles are known.

The awkward part is the grid. No lead on a TO-18 lands on a 2.54 mm grid node, so a board laid out on a 0.05 in or 0.1 in grid will have three off-grid pads in the middle of it. Place the footprint origin at the pin circle centre and let the router deal with it rather than nudging pads onto the grid.

For the keepout, the flange runs to 5.84 mm maximum, so a 6.0 mm circle covers the body. Add the Bivar mount and it becomes 6.5 mm.

Where TO-18 still wins

• Hermeticity or military screening is a requirement. MIL-PRF-19500/255 covers the 2N2221A and 2N2222A in TO-18 and offers four encapsulated quality levels: JAN, JANTX, JANTXV and JANS, plus two unencapsulated die levels. Radiation hardness assured lots carry an extra prefix letter.
• The device needs an optical aperture. Photodiodes, IR emitters and laser diodes use the same header with a window or lens in place of the flat cap. Laser diode catalogs call this the 5.6 mm can, which is the flange diameter, not the 4.7 mm cap that transistor datasheets quote.
• The case must be a circuit node. That is TO-72, the four-lead member, with the fourth lead bonded to the can for RF shielding.
• You need the same die in three formats. InterFET ships the 2N4416 JFET as a hermetic TO-72 for military work, as PN4416 in TO-92 and as SMP4416 in surface mount, from one datasheet.

It stops winning the moment cost or dissipation dominates. A plastic package handles more power per dollar, and above roughly half a watt in free air the metal can has nothing left to give.

Cost, lead time and sourcing traps

Part	Grade	DigiKey number	Unit price	Factory lead time	Stock at listing
2N2222A PBFREE, Central Semiconductor	Commercial	1514-2N2222APBFREE-ND	$3.29 at 1, $1.11977 at 1,000	9 weeks	14,981
JAN2N2222A, Microchip	JAN, MIL-PRF-19500/255	1086-2323-ND	$2.39 at 1, $2.22 at 100	22 weeks	0
JANTX2N2222A, Microsemi	JANTX	1086-2675-ND	$3.95714	not listed	not listed
JANS2N2907A, Microsemi	JANS	1086-15273-ND	$71.14	not listed	not listed

Screening dominates the price. A commercial TO-18 NPN lands near $1.12 in thousands, JANTX screening on the same family lists near $3.96, and a JANS PNP in the same can lists at $71.14. Lead time moves the same way, from 9 weeks commercial to 22 weeks for JAN.

One catalog trap is worth knowing. The DigiKey listing for JAN2N2222A gives the package as TO-206AA, TO-18-3 metal can in one field and TO-218 in the supplier device package field. A parametric search filtered on TO-18 will miss parts mistagged this way, and a search on TO-218 will surface a small-signal transistor among power devices.

Frequently asked questions

What is a TO-18 package?

TO-18 is a hermetically sealed metal can for semiconductors with up to three leads. A Kovar header carries the die, glass seals insulate the leads, and a plated steel cap is welded over the top. The cap measures 4.52 to 4.95 mm across and the leads sit on a 2.54 mm pin circle.

Is TO-18 the same as TO-206AA?

Yes. JEDEC consolidated the 2.54 mm pin circle header outlines into the TO-206 family and TO-18 became TO-206AA. Datasheets use both names, sometimes on the same page. Distributor package fields often show them together as TO-206AA, TO-18-3 metal can.

What is the difference between TO-18 and TO-46?

Cap height, and nothing else. TO-18 stands 4.83 mm tall while TO-46 stands 1.90 mm. Both use the same 2.54 mm pin circle and the same header diameter, so they share a footprint. TO-52 sits between them at 3.30 mm. In current nomenclature they are TO-206AA, TO-206AB and TO-206AC.

How much power can a TO-18 transistor dissipate?

About 400 to 500 mW at 25 °C ambient with no heatsinking, set by a junction-to-ambient resistance near 300 to 325 °C/W. Case-referenced ratings of 1.0 to 1.8 W assume the flange is held at 25 °C, which a normal board mounting does not achieve.

Why is a TO-18 transistor more expensive than a TO-92?

Materials and process. A TO-18 uses a Kovar header, individual glass to metal lead seals and a welded cap, then gets leak tested. Plastic packages are molded in one step and never leak tested. Military screening adds more on top, taking a commercial part from about a dollar to tens of dollars.

Is the TO-18 case connected to the collector?

Check the datasheet rather than assuming. onsemi defines only three terminals for CASE 206AA Style 1, so the can is not a listed node. When the case genuinely must be a circuit connection, the four-lead TO-72 variant exists for exactly that, with the extra lead bonded to the can.

What to do next

If the requirement is a signature on a hi-rel drawing, specify by screening level first and package second: JANTX for most military ground and airborne work, JANS only where the program mandates it, and budget 22 weeks. If the requirement is only a small-signal transistor, a plastic package does the same job for a tenth of the price.

Draw the footprint from the pin circle centre with a 0.73 mm finished hole and 1.33 mm pads, take the angular lead positions from the device drawing rather than the outline, and add mechanical support if the assembly sees vibration. The glass seals will not tell you when they have cracked.

Internal links proposed

• [INTERNAL LINK: TO-92 package dimensions and pinouts → TO-92 reference page]
• [INTERNAL LINK: hermetic versus plastic semiconductor packages → packaging technology guide]
• [INTERNAL LINK: MIL-PRF-19500 screening levels explained → high reliability sourcing guide]
• [INTERNAL LINK: calculating junction temperature from thermal resistance → thermal design fundamentals]
• [INTERNAL LINK: through-hole land pattern rules in IPC-2221 → PCB footprint design guide]

External sources

• onsemi 2N2222A datasheet Rev 2, CASE 206AA Issue A: https://web.mit.edu/6.101/www/reference/2N2222A.pdf
• Central Semiconductor TO-18 package detail and material composition: https://www.centralsemi.com/PDFs/case/TO_18_PD.PDF
• onsemi AN1040/D Rev 5, Mounting Considerations For Power Semiconductors: https://www.onsemi.cn/download/application-notes/pdf/an1040-d.pdf
• NASA NEPP, Hermeticity Leak Testing, leak rate limits under MIL-STD-750 Method 1071: https://nepp.nasa.gov/docs/etw/2013/Tue_June11_2013/1630_McManus_Pressnell_Hermeticity%20Leak%20Testing.pdf
• STMicroelectronics 2N2219A / 2N2222A datasheet: https://docs.rs-online.com/66ed/0900766b813647d2.pdf
• InterFET 2N4416 / 2N4416A datasheet: https://www.interfet.com/jfet-datasheets/jfet-2n4416-2n4416a-interfet.pdf