A narrow-body SOIC land pattern uses 0.60 mm × 1.55 mm pads on 1.27 mm pitch, with 5.40 mm between the two pad rows measured center to center. Texas Instruments and Microchip both publish exactly those numbers. Feed the same JEDEC MS-012 AA package into the IPC-7351B equations at Nominal density and you get 0.61 mm × 2.18 mm pads at 4.74 mm spacing. Both answers are defensible. Here is when each one wins.

Key takeaways

• Narrow-body SOIC (JEDEC MS-012, 1.75 mm max height): pads 0.60 mm × 1.55 mm, pitch 1.27 mm, row spacing 5.40 mm. TI and Microchip publish identical values for 8, 14 and 16 leads.
• Wide-body SOIC (JEDEC MS-013, 2.65 mm max height): pads 0.60 mm × 2.00 mm, row spacing 9.30 mm.
• IPC-7351B at Nominal density, computed from the MS-012 AA limits, returns a 2.18 mm pad. That is 0.63 mm longer than the datasheet pad, and nearly all of the extra copper sits at the heel.
• One term drives the gap: the 0.41 mm to 1.27 mm foot-length tolerance on the JEDEC drawing, which enters the heel equation as a 2.11 mm root-sum-square penalty.
• Use the manufacturer pattern for volume reflow, IPC Level A (Most) for hand assembly and rework, and always work from a drawing revision rather than a package name.

SOIC land pattern dimensions at a glance

Three geometries cover most SOIC designs. Z is the toe-to-toe dimension across the full pattern, G is the heel-to-heel gap between opposing pad rows, and C is the distance between pad-row centers. Z, G and the pad width X are the three quantities IPC-7351B actually solves for; everything else is derived.

Table 1. Published and calculated SOIC land patterns, all values in millimeters

Package	JEDEC	Lead span L	Pitch	Pad X × Y	C	Z	G
SOIC-8 / -14 / -16, 3.90 mm body (TI, Microchip drawings)	MS-012	5.80–6.19	1.27	0.60 × 1.55	5.40	6.95	3.85
SOIC-16 wide, 7.50 mm body (TI DW0016A)	MS-013	9.97–10.63	1.27	0.60 × 2.00	9.30	11.30	7.30
SOIC-8, IPC-7351B Nominal (calculated below)	MS-012 AA	5.80–6.19	1.27	0.61 × 2.18	4.74	6.91	2.56

The narrow-body row is not an average of several vendors. TI drawing 4214825/C and Microchip drawing C04-2057-C2X Rev K specify the same pad, spacing and pitch to two decimal places, and Microchip repeats those values on its 14-lead narrow-body drawings. If your library holds a different narrow-body SOIC pattern, someone chose to deviate.

[IMAGE 1: annotated SOIC-8 land pattern showing X, Y, C, Z, G and the 1.27 mm pitch, with the package outline ghosted over it | alt: “SOIC land pattern dimensions X, Y, C, Z and G annotated on an 8-lead footprint”]

Identify the package before you draw anything

The label on a schematic symbol carries almost no geometric information. An 8-pin SOIC can be MS-012 with a 3.90 mm body and a 1.75 mm height limit, or MS-013 with a 7.50 mm body and a 2.65 mm limit, and the two patterns differ by 4.35 mm across the toes. Pull the mechanical drawing for the exact orderable part number and read its revision code.

Four numbers from that drawing feed every equation that follows. L is the lead span, tip to tip, given as a range. T is the foot length, also a range. W is the lead width. The pitch is a basic dimension and carries no tolerance. For the TI D0008A drawing those values are L = 5.80 to 6.19 mm, T = 0.41 to 1.27 mm, W = 0.31 to 0.51 mm, pitch 1.27 mm.

IPC library names encode the same information, and they are widely misread. In SOIC127P600X175-8N, 127P is the 1.27 mm pitch, 600 is the nominal lead span of 6.00 mm, 175 is the 1.75 mm body height, 8 is the pin count, and N marks Nominal density. The 600 is not the body width; the body is 3.90 mm wide. Sizing a footprint on that misreading produces pads that sit under the package body.

The IPC-7351B equations, worked for a SOIC-8

IPC-7351B solves three dimensions at maximum material condition. Each combines a package limit, a solder fillet allowance, and a root-sum-square of the tolerances that can move the lead relative to the copper.

Zmax = Lmin + 2Jt + √(CL² + F² + P²)

Gmin = Smax − 2Jh − √(CS² + F² + P²)

Xmax = Wmin + 2Js + √(CW² + F² + P²)

Jt, Jh and Js are the toe, heel and side fillet allowances, and they are the only values that change between density levels. S is the inboard span, where Smax = Lmax − 2Tmin and Smin = Lmin − 2Tmax. CL, CS and CW are the corresponding package tolerances. F is the fabrication tolerance and P the placement tolerance; IPC uses 0.10 mm for each.

Running the D0008A limits through those equations gives the numbers below. Smax is 5.37 mm, Smin is 3.26 mm, so CS is 2.11 mm. CL is 0.39 mm and CW is 0.20 mm.

Table 2. IPC-7351B density levels applied to JEDEC MS-012 AA, values in millimeters

Density level	Jt	Jh	Js	Courtyard excess	Pad X × Y	C	Z	G
Most (Level A)	0.55	0.45	0.05	0.50	0.65 × 2.48	4.84	7.31	2.36
Nominal (Level B)	0.35	0.35	0.03	0.25	0.61 × 2.18	4.74	6.91	2.56
Least (Level C)	0.15	0.25	0.01	0.10	0.57 × 1.88	4.64	6.51	2.76

Two behaviors in that table surprise people. The pad grows toward the toe as density relaxes, while G moves the other way, so the Least pattern has a wider heel gap than the Most pattern. And the pad width barely moves: 0.08 mm separates Level A from Level C, because the side fillet allowance is small next to the 0.20 mm lead-width tolerance.

Why the calculated pad is longer than the one on the datasheet

Three respected sources describe the same SOIC-8 land pattern three different ways. Their toe positions agree to within 0.05 mm. Their heels do not.

Table 3. Same package, three sources, millimeters and square millimeters

Source	Pad X × Y	C	Z	G	Copper per pad
TI 4214825/C and Microchip C04-2057-C2X Rev K	0.60 × 1.55	5.40	6.95	3.85	0.93 mm²
KiCad SOIC-8_3.9×4.9mm_P1.27mm	0.60 × 1.95	4.95	6.90	3.00	1.17 mm²
IPC-7351B Nominal, calculated	0.61 × 2.18	4.74	6.91	2.56	1.33 mm²

The spread is entirely a heel argument, and the CS term explains it. Because the MS-012 drawing tolerances the foot length from 0.41 mm to 1.27 mm, the inboard span S can vary by 2.11 mm, and that number dominates the root-sum-square in the Gmin equation. IPC answers by pushing copper inward until the heel fillet is guaranteed for the worst-case short foot, which costs 43 percent more copper per pad than the TI pattern, over eight pads.

Manufacturers answer differently. NXP states the rule plainly in AN2409: center the foot on the pad and extend roughly 0.50 mm past it at both heel and toe, and size the pad width at about 60 percent of pitch, which is where 0.60 mm at 1.27 mm pitch and 0.38 mm at 0.65 mm pitch come from. That approach targets the nominal lead, not the worst-case one, and it keeps copper from creeping under the package body.

The decision rule is short. For automated reflow with vision placement, use the manufacturer pattern; it is the geometry the package supplier has qualified. For hand assembly, rework-heavy prototypes, or any board where an inspector must see a heel fillet under IPC-A-610, take the IPC Level A pattern and accept the extra 1.5 mm of length across the footprint. For 0.65 mm-pitch wide-body parts such as the 32-lead and 54-lead SOICs, drop to Level B or C, because Level A pads leave a copper gap that solder paste will bridge.

[IMAGE 2: overlay of the three SOIC-8 patterns from Table 3 on a common origin, heel gaps highlighted | alt: “Comparison of TI, KiCad and IPC-7351B SOIC land pattern heel dimensions”]

Courtyard, solder mask and stencil

The courtyard is the keepout that stops two adjacent parts from colliding. Take the larger of the land-pattern extent and the package body extent on each axis, add the courtyard excess from Table 2, then round outward to a 0.05 mm grid. For a Nominal SOIC-8 that gives roughly 7.45 mm across the pads by 5.50 mm along the body, driven by the 5.00 mm maximum body length.

TI specifies the solder mask as non-solder-mask-defined with 0.07 mm of clearance all around each pad. That is a deliberate margin, since mask registration on a standard process runs about ±0.05 mm. Pulling the mask back further starts thinning the web between pads, and NXP warns that thin webbing lifts off the laminate during reflow.

For stencils, TI dimensions its paste example for 0.125 mm foil, and NXP recommends 0.125 mm to 0.150 mm for 1.27 mm pitch and 0.100 mm to 0.125 mm for 0.65 mm pitch. Copper-to-copper gap on a 1.27 mm-pitch SOIC is 0.67 mm with 0.60 mm pads, which is generous. Bridging on these packages is nearly always a paste volume or placement problem rather than a footprint problem.

Exposed-pad SOIC needs three extra numbers

SOIC-EP variants add a thermal land under the body, and the lead pads usually have to shrink to make room. NXP requires at least 0.25 mm of clearance between the outer edge of the thermal land and the inner edge of the lead pads. KiCad follows the same logic in its official library: the SOIC-8-1EP footprint built around a 2.514 × 3.20 mm thermal pad carries 1.625 mm lead pads instead of the 1.95 mm used on the non-EP part.

Three more values matter for the thermal land. Print 50 to 80 percent paste coverage through a windowed aperture rather than one opening, which lands the finished joint at 80 to 90 percent of pad area. Make the stencil aperture 0.25 mm smaller than the copper pad for registration. Use 0.30 mm to 0.33 mm thermal vias on a 1.2 mm grid, and if the plating does not close the barrel, tent them with a mask opening at least 0.10 mm larger than the via.

Five mistakes that cause real assembly defects

• Applying a wide-body land pattern to a narrow-body part. A 9.30 mm row spacing under a 6.00 mm lead span leaves every toe hanging off its pad.
• Trusting the name SOIC-8. MS-012, MS-013 and vendor-specific SO-8 outlines all ship under that label, and the KiCad library alone carries SO-8 pads of 1.75 mm against SOIC-8 pads of 1.95 mm.
• Using Level A pads on 0.65 mm-pitch SOIC. The 0.05 mm side fillet plus tolerance leaves too little copper gap for reliable paste release.
• Printing a single full-size aperture over an exposed pad. The package floats, voiding climbs, and the lead joints starve.
• Placing the pin-1 marker outside the courtyard, where the silkscreen gets covered by the part. Reversed placement remains the most common orientation defect on gull-wing parts.

Frequently asked questions

What is the standard SOIC-8 footprint size?

For a narrow-body SOIC-8 to JEDEC MS-012 AA, the published land pattern is eight pads of 0.60 mm × 1.55 mm on 1.27 mm pitch, with 5.40 mm between pad-row centers. That gives 6.95 mm across the toes and a 3.85 mm heel gap. TI and Microchip specify identical values on their current drawings.

What is the difference between a footprint and a land pattern?

Land pattern is the IPC term for the copper geometry alone: pads, sizes, positions. Footprint is the EDA term for the whole library object, which adds silkscreen, assembly outline, courtyard, solder mask and paste layers, and the 3D model reference. IPC-7351B standardizes the land pattern; your library rules govern the rest.

Is IPC-7351B still the current land pattern standard?

Yes. Revision B was published in June 2010 and remains the released version through 2026. It replaced IPC-SM-782A, added flat-lead and DFN families, and introduced the padstack naming convention that EDA libraries now use.

Which density level should I choose for a SOIC?

Level B (Nominal) for standard reflow production. Level A (Most) when the board will be hand-soldered or reworked, or when fillet inspection is a contractual requirement. Level C (Least) only for high-density boards, and only after your assembler confirms the process window.

Can I use the same land pattern for SOIC and SOP?

Only if the lead span, foot length and lead width match. Many SOP parts share the 1.27 mm pitch but differ in span, and 0.65 mm-pitch SOP and SSOP parts need a 0.38 mm pad width. Compare the four drawing dimensions before reusing anything.

What to do next

Open the mechanical drawing for the exact orderable part, record L, T, W and pitch, and check them against Table 1. If they match the MS-012 or MS-013 rows, use the manufacturer pattern and move on. If they do not, run the three equations at Level B, then compare your result to Table 3 to confirm the toe lands near 6.90 mm for a narrow body. Send the finished pattern to your assembler with the density level named, because that single word tells them whether you designed for their placement machine or for a soldering iron.

Sources

• Texas Instruments, D0008A package drawing 4214825/C, 02/2019 (SOIC, 1.75 mm max height) – https://www.ti.com/lit/pdf/msoi002k
• Texas Instruments, DW0016A package drawing 4220721/A, 07/2016 (SOIC, 2.65 mm max height) – https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/14/DW16drawing.pdf
• Microchip, 8-Lead Plastic Small Outline (C2X) recommended land pattern, drawing C04-2057-C2X Rev K, in LR645 data sheet DS20005384B – https://ww1.microchip.com/downloads/aemDocuments/documents/APID/ProductDocuments/DataSheets/LR645-Data-Sheet-DS20005384.pdf
• NXP / Freescale, AN2409 Rev 3.0 (10/2014), Small Outline Integrated Circuit (SOIC) Package – https://www.nxp.com/docs/en/application-note/AN2409.pdf
• IPC-7351B, Generic Requirements for Surface Mount Design and Land Pattern Standard, June 2010 – https://shop.ipc.org/ipc-7351/ipc-7351-standard-only/Revision-b/english
• KiCad official footprint library, SOIC-8_3.9×4.9mm_P1.27mm and SOIC-8-1EP variants – https://github.com/KiCad/kicad-footprints/blob/master/Package_SO.pretty/SOIC-8_3.9×4.9mm_P1.27mm.kicad_mod
• SnapMagic (SnapEDA), The IPC-7351 Specification Explained: SOIC Components (solder fillet table) – https://blog.snapeda.com/2015/07/13/the-ipc-7351-specification-explained-soic-components/