A SIL package puts every lead in one row along one edge of the body, so the part stands upright on the board. SIL and SIP name the same lead format. It survives in resistor networks, reed relays, DC/DC modules, and switches because one row of leads is cheap and vertical mounting buys board width. The specs below decide whether it fits.
Key takeaways
- SIL (single in-line) and SIP (single in-line package) describe the identical lead arrangement; NXP uses SIL as the package type code and SIP as the style code on the same drawing.
- The 2.54 mm pitch is a convention, not a rule — NXP’s SIL4 (SOT1188-3) runs 1.8 mm.
- For resistor networks, the package power rating binds before the per-element rating, usually by a factor of about 1.4.
- Bourns and CTS both build conformal SIP networks on the same footprint but use incompatible circuit code numbers.
- Verify per-element power and maximum working voltage before accepting any second source; a 4.7 kΩ CTS element is voltage-limited to about 21.7 V, not the 50 V headline.
[IMAGE 1: labeled outline of an 8-pin single in-line resistor network standing on a PCB, calling out 2.54 mm pitch, 5.08 mm maximum height, 2.49 mm maximum body thickness | alt: “SIL package dimensions for an 8-pin single in-line resistor network at 2.54 mm lead pitch”]
What a SIL package is
A SIL package is a component body with all leads leaving one edge in a single straight row, normally on 2.54 mm centers, inserted through-hole so the body stands vertical to the board. SIP is the same format under a different name. Pin counts typically run from 3 to 14.
That vertical orientation is the whole point. A DIP lies flat and consumes board area proportional to length times row spacing. A SIL consumes length times body thickness — 2.49 mm maximum for the Bourns 4600X series, per the package drawing in revision 10/1/20 — and spends its budget in the Z axis instead.
SIL, SIP, ZIP, DIP: which name means what
The naming is regional and inconsistent, which is why the same part shows up under three labels.
- SIL / SIP — one row of leads, one edge. European datasheets and distributors favor SIL; US and Japanese datasheets favor SIP.
- ZIP — zig-zag in-line. Leads leave the same edge but alternate front and back, so the visible spacing halves while the insertion pattern stays on a 2.54 mm grid.
- DIP / DIL — two parallel rows on opposite edges.
- SiP (lowercase i) — system in package, an entirely different concept covering multiple dice in one body. Watch the capitalization in supplier search fields.
NXP’s package information sheet for SOT1188-3 settles the SIL-versus-SIP argument in one table: the package type descriptive code is SIL4, while the package style descriptive code is SIP. Same part, both names, one document.
[INTERNAL LINK: dual in-line package pinouts and footprints -> DIP package guide]
Where the SIL package still ships
Four device families keep this format in current production. The numbers below come from the manufacturers’ own documents.
| Device family | Example part | Pins × pitch | Body D × W × H (mm) | Headline ratings | Source doc |
| Conformal thick-film resistor network | Bourns 4608X-101-472LF | 8 × 2.54 ± 0.07 mm | 2.49 max × 20.27 max × 5.08 max | 7 bussed 4.7 kΩ ±2 %; 0.20 W/element and 1.00 W/package at 70 °C; 100 V max | 4600X REV. 10/1/20 |
| Conformal thick-film resistor network | CTS 770101472P | 10 × 2.54 ± 0.20 mm | 2.50 max × 25.40 max × 4.95 max | 9 bussed 4.7 kΩ ±2 %; 0.100 W/element and 0.900 W/package at 70 °C | CTS DOC# 008-0339-0 |
| Reed relay, 1 Form A | Pickering 113-1-A-5/2D | 4 × 2.54 mm | 3.7 × 12.5 × 6.6 | 10 W, 0.5 A, 200 V max switching; 5 V/500 Ω coil; 0.5 ms operate | Series 113 Issue 1.3 |
| Reed relay, 2 Form A | Pickering 113-2-A-5/2D | 6 × 2.0 mm | 3.7 × 12.5 × 8.9 | 10 W per contact; 5 V/150 Ω coil | Series 113 Issue 1.3 |
| Switching regulator module (SIP3) | RECOM R-78E5.0-1.0 | 3, TO-220 compatible | 11.6 × 8.5 × 10.4 | 7–28 V in, 5 V/1.0 A out, up to 91 % efficiency | R-78E-1.0 datasheet |
| Molded semiconductor SIL4 | NXP SOT1188-3 | 4 × 1.8 mm | 11.0 × 7.4 × 1.95 body | Plastic, through-hole, issue date 14-12-2021 | SOT1188-3, 5 May 2022 |
Two things fall out of that table. Pitch is not fixed at 2.54 mm — Pickering’s 2 Form A relay uses 2.0 mm spacing and NXP’s SIL4 uses 1.8 mm. And height varies by more than 5:1 across the format, from a 4.95 mm resistor network to a 10.4 mm regulator module, so a SIL choice is really a height-budget choice.
Bussed, isolated, dual terminator — and the code collision
Resistor networks are where most SIL package decisions go wrong, because three different internal circuits ship in identical bodies with identical footprints.
| Circuit | What it does | Bourns 4600X code | CTS 770 code | Elements in an 8-pin part |
| Bussed | All elements share pin 1 as a common bus | 101 | 1 | 7 |
| Isolated | Independent elements between pin pairs | 102 | 3 | 4 |
| Dual terminator | Paired series elements between pins 1 and 8 | 104 | 5 | 12 (terminating 6 lines) |
Bourns 102 means isolated. CTS 3 means isolated. A cross-reference done on the middle digits alone produces a part that fits the board, passes visual inspection, and shorts every pull-up together. This is the single most expensive mistake available with this package.
The dual-terminator variant adds an orientation hazard: in the Bourns 4608X-104, pin 1 and pin 8 are common for ground and power respectively. The package has no notch. Pin 1 is marked with a dot and nothing else.
[IMAGE 2: three schematics side by side showing bussed, isolated, and dual-terminator SIL resistor networks with pin numbering | alt: “Bussed, isolated, and dual terminator circuits in a SIL package resistor network”]
[INTERNAL LINK: bussed vs isolated resistor arrays -> resistor network circuit types]
Power ratings: the package limit binds first
Take the Bourns 4608X-101 — eight pins, seven bussed elements. Per the datasheet, each bussed element is rated 0.20 W at 70 °C. Seven elements at full rating is 1.40 W. The package rating for the 4608X is 1.00 W at 70 °C.
The package wins. You get 1.00 W ÷ 7 ≈ 0.143 W per element if all seven run simultaneously — a 29 % derate against the element number printed two lines higher in the same datasheet.
Then apply ambient derating: both the Bourns and CTS derating curves fall linearly from full rating at 70 °C to zero at 125 °C. At 100 °C ambient you have roughly 45 % of the 70 °C figure left, or about 0.065 W per element on that same 4608X-101.
Voltage has a parallel trap. Bourns specifies a flat 100 V maximum operating voltage for the 4600X. CTS specifies the maximum working voltage for the 770 Series as the lower of √(P × R) and 50 V. For a 4.7 kΩ element at the 100 mW rating:
√(0.1 W × 4700 Ω) = √470 = 21.7 V
Not 50 V, and not 100 V. If the network is pulling up a 24 V industrial input, the CTS part is out of spec and the Bourns part is not.
Drawing the footprint: hole and pad from IPC-7251
SIL leads are rectangular, not round, so hole sizing starts from the lead diagonal at maximum material condition. The Bourns 4600X lead is 0.50 ± 0.10 mm by 0.254 ± 0.05 mm, giving a maximum cross-section of 0.60 mm × 0.304 mm.
Diagonal = √(0.60² + 0.304²) = 0.673 mm
IPC-7251 sets the finished hole from the maximum lead dimension plus a density-level allowance:
| Density level | Allowance | Finished hole for a 4600X lead | Pad diameter at 0.05 mm annular ring |
| A (maximum, low density) | +0.25 mm | 0.92 mm | 1.62 mm |
| B (nominal) | +0.20 mm | 0.87 mm → drill 0.9 mm | 1.47 mm → 1.5 mm |
| C (minimum, high density) | +0.15 mm | 0.82 mm | 1.32 mm |
At Level B the 1.5 mm pad leaves 1.04 mm of copper-to-copper clearance on a 2.54 mm pitch, which is comfortable for a Class 2 board.
Run the same arithmetic on the CTS 770 lead (0.50 ± 0.10 mm × 0.25 ± 0.10 mm, maximum diagonal 0.695 mm) and Level B gives 0.895 mm — the same 0.9 mm drill. One footprint genuinely serves both vendors, which is exactly why the circuit-code mismatch above is so easy to miss.
[IMAGE 3: hole and pad construction for a rectangular SIL lead showing lead diagonal, finished hole, annular ring, and fabrication allowance | alt: “IPC-7251 hole and pad sizing for a SIL package rectangular lead”]
[INTERNAL LINK: IPC-7251 through-hole land patterns -> through-hole footprint design]
Failure modes that generate returns
Reversed insertion. No notch, no keying, one dot. A reversed bussed network moves the common bus from pin 1 to pin 8, which on most layouts ties the bus to a signal net instead of a rail. Add a silkscreen pin-1 chevron and a square pad on pin 1.
Silent circuit substitution. Bussed and isolated parts share body, length, and marking format. The marking distinguishes them: a Bourns 4608X-102 marks as 8X-2-RC. Read the middle digit at incoming inspection.
Mechanical fatigue. A SIL body is cantilevered off one row of leads, so it takes bending loads that a DIP shares across two rows. The CTS 770 is qualified to 100 g at 1 ms shock and 20 g from 10 Hz to 2000 Hz; the Pickering 113 relay to 50 g shock and 20 g vibration. Above those levels, bond or brace tall SIL parts.
Coil polarity on relays. Pickering’s Series 113 datasheet is explicit: where the optional internal suppression diode is fitted, coil polarity must follow the + symbol on the schematic. Reversed drive puts the diode straight across the supply.
Magnetic interaction between adjacent relays. Packing SIL reed relays shoulder to shoulder changes their operate and release voltages. Pickering rates its internally mu-metal-screened parts at roughly 5 % interaction against about 30 % for typical unscreened industry relays, and specifies stacking on 0.15 × 0.5 inch pitch for the Series 113.
Solder profile. The CTS 770 leads are copper-plated iron with a SnAgCu finish, reflow-rated per JEDEC J-STD-020 to 260 °C maximum. Pickering caps the Series 113 at 270 °C for 10 s. Hand-rework on a stuffed board routinely exceeds both.
Second sourcing, lifecycle, and cost
SIL parts are cheap and long-lived, which breeds complacency. Current DigiKey listings show 4608X-101-472LF at about $0.33 in single quantity with thousands in stock — but the 6-pin 4606X-101-472LF sits at zero stock against a 24-week manufacturer standard lead time, and the tin-lead 4608X-101-472 is flagged obsolete with the lead-free part as its direct substitute.
That pattern repeats across the format: high-volume pin counts stay stocked, odd pin counts do not. Before committing, check the exact pin count you need rather than the series.
A qualified second source for a SIL resistor network needs four checks, not one: circuit code mapped by schematic and not by number, per-element power at 70 °C, package power at 70 °C, and the maximum working voltage rule. Bourns and CTS differ on three of those four while sharing the footprint.
[INTERNAL LINK: component obsolescence and second-source qualification -> lifecycle management]
SIL package FAQ
What does SIL stand for in electronics?
SIL stands for single in-line, describing a package whose leads all emerge from one edge of the body in a single row. Note the collision: in functional safety, SIL means Safety Integrity Level under IEC 61508. The two are unrelated, and search results mix them freely.
Is a SIL package the same as a SIP package?
Yes. Both describe one row of leads on one edge. NXP’s SOT1188-3 package sheet lists SIL4 as the package type descriptive code and SIP as the package style descriptive code for the same part. Regional preference decides which appears on a given datasheet.
What is the pin pitch of a SIL package?
2.54 mm is the common case — Bourns specifies 2.54 ± 0.07 mm non-accumulative for the 4600X, CTS 2.54 ± 0.20 mm for the 770. It is not universal. Pickering’s 2 Form A relay uses 2.0 mm, and NXP’s SIL4 uses 1.8 mm.
What is the difference between SIL and DIP packages?
DIP has two lead rows on opposite edges and lies flat; SIL has one row and stands vertical. DIP gives higher pin counts and two-sided mechanical support. SIL gives a narrower board footprint at the cost of height and a weaker single-row mechanical anchor.
How many pins does a SIL package have?
Typically 3 to 14. Bourns builds the 4600X in 4 through 14 pins, CTS the 770 in 4 through 12, RECOM’s SIP3 regulator uses 3, and Pickering’s Series 113 relays use 4 or 6. Both odd and even counts exist.
Is a SIL package through-hole or surface mount?
Through-hole is the default; NXP classifies SOT1188-3 as through-hole mount. Surface-mount variants exist — Bourns lists 4300H/M/R and 4600H/M/X as surface-mount SIP profiles — so check the mounting method code on the package drawing rather than assuming.
What to do next
If the part is a resistor network and your board is width-constrained but has vertical clearance above 6 mm, the SIL package is the right call — specify by schematic, size the drill at 0.9 mm for a 2.54 mm-pitch lead at IPC-7251 Level B, and budget power against the package rating, not the element rating.
If ambient exceeds 85 °C or elements must carry more than about 0.1 W each, move to discrete resistors or a larger array; the derating curve to zero at 125 °C removes the headroom you thought you had.
If you are qualifying a second source, do not accept a cross-reference table. Pull both datasheets, map the schematics visually, and compare per-element power and the working-voltage rule. On this package, the footprint matching means nothing.
[IMAGE 4: Pickering 113 and 113SP pinouts overlaid on a shared PCB footprint | alt: “SIL package reed relay pinouts sharing one PCB footprint”]
Primary sources
- Bourns 4600X Series datasheet, REV. 10/1/20 — https://www.bourns.com/docs/Product-Datasheets/4600x.pdf
- CTS 770 Series, Conformal Coated SIP Resistor Network, DOC# 008-0339-0 — https://ctscorp.com/Files/DataSheets/Passives/Resistors/CTS-Resistors-770-Series-Datasheet.pdf
- Pickering Electronics Series 113 SIL/SIP Reed Relays, Issue 1.3, Jan 2022 — https://www.farnell.com/datasheets/3715995.pdf
- NXP SOT1188-3 package information, 5 May 2022 — https://www.nxp.com/docs/en/package-information/SOT1188-3.pdf
- RECOM R-78E-1.0 series datasheet — https://recom-power.com/pdf/Innoline/R-78E-1.0.pdf
- IPC-7251 / IPC-2222 through-hole density-level sizing summary — https://www.nwengineeringllc.com/article/plated-through-hole-size-for-pcb-component-leads.php
