If a datasheet says LFCSP, MLF, MLP, HVQFN, or SON, you are looking at a QFN-family part under a vendor’s private name. The QFN package types that actually differ do so along three axes: how many sides carry pads, whether there is an exposed thermal pad, and whether the side flanks are solderable for inspection. This guide maps every alias to its real type and JEDEC outline, then covers the variant choices that change your layout.
Key takeaways
- The names are mostly marketing. IPC-7093 explicitly treats QFN, DFN, SON, LGA, MLP, and MLF as one component class with shared design rules, differing largely by supplier branding.
- Sides decide the base type: QFN has pads on all four sides (JEDEC MO-220), DFN/SON on two (JEDEC MO-229/MO-241). Everything else is a size, height, or process variant.
- Leadless is why QFN exists: eliminating leads cuts parasitic inductance to roughly 1 to 3 nH per pin against 5 to 10 nH for leaded packages, per pcbsync’s package data.
- Automotive needs a wettable flank. Standard QFN flanks are hidden, so a step-cut or dimpled, tin-plated flank is added to form a visible fillet for optical inspection.
- The exposed pad is a functional connection, not an anchor. IPC-A-610 caps voiding under it at 25 percent for production acceptance.
What “QFN” actually means
A QFN (Quad Flat No-lead) is a leadless surface-mount package: flat copper terminals sit along the bottom perimeter, and a large exposed pad (EPAD) usually occupies the center of the underside. The terminals replace a QFP’s gull-wing leads, and the EPAD solders directly to a PCB thermal land, giving a short, low-resistance path from die to copper.
The industry’s umbrella term is bottom-termination component (BTC), any package whose connections are metallized terminals on the bottom, covered generically by IPC-7093. That family includes QFN, DFN, SON, and LGA, plus multi-row and advanced versions.
Two properties make QFN attractive. Removing the leads shortens every connection, dropping parasitic inductance to about 1 to 3 nH per pin versus 5 to 10 nH for leaded parts. And the leadless outline is small: a 32-lead QFN occupies roughly 25 mm-squared in a 5 by 5 mm body against about 81 mm-squared for a 9 by 9 mm 32-lead QFP, a footprint cut near 70 percent, per published comparisons.
The QFN naming cross-reference
The single most useful thing to know about QFN is that a dozen names describe the same construction. The table below maps each alias to its generic type and JEDEC outline.
| Name / alias | Origin | Generic type | Outline / notes |
| QFN | JEDEC generic | Quad, 4-sided | MO-220; body 2×2 to 12×12 mm |
| DFN | JEDEC generic | Dual, 2-sided | MO-229 / MO-241 |
| SON | Generic | Dual, 2-sided | Same as DFN |
| LFCSP | Analog Devices | QFN | ADI’s brand for QFN |
| MLF / MicroLeadFrame | Amkor | QFN or DFN | Amkor trademark |
| MLP | onsemi / Fairchild | QFN or DFN | Micro Lead Package |
| LPCC | Generic | QFN | Leadless Plastic Chip Carrier |
| LLP | National / TI | QFN | Leadless Leadframe Package |
| HVQFN | NXP | QFN | NXP’s very-thin QFN family |
| VQFN / WQFN / UQFN | JEDEC height codes | QFN | Very / very-very / ultra thin |
| aQFN, DRQFN, MRQFN | Generic | Multi-row QFN | Higher I/O, approaches CSP |
| Flip-chip QFN | Generic | QFN | Bumped die, RF/wireless |
[IMAGE 1: underside of a QFN showing perimeter terminals and central exposed pad, beside a two-sided DFN | alt: “QFN package types showing quad no-lead exposed pad versus a two-sided DFN”]
QFN vs DFN vs QFP: the real structural differences
The base decision is sides and leads. A DFN is a QFN with terminals on only two opposing edges, which suits low-pin-count parts — power management, current-sense amplifiers, small logic — where a full quad perimeter would waste space. SON (Small Outline No-lead) is the same thing under a different name.
A QFP is the leaded ancestor: gull-wing leads on all four sides that a camera can inspect and a tech can rework, at the cost of size and lead inductance. The table contrasts the three.
| Feature | QFN | DFN / SON | QFP |
| Pads / leads | 4 sides, no leads | 2 sides, no leads | 4 sides, gull-wing |
| Exposed thermal pad | Usually yes | Usually yes | Optional |
| Inductance per pin | ~1–3 nH | ~1–3 nH | ~5–10 nH |
| Footprint | Smallest | Small | Largest |
| Visual inspection | Hard (flank needed) | Hard (flank needed) | Easy |
| Typical pitch | 0.4–0.65 mm | 0.4–0.5 mm | 0.4–0.8 mm |
| JEDEC outline | MO-220 | MO-229 / MO-241 | MS-026 family |
Variant axes that change your design
Beyond sides, four axes distinguish QFN variants and each touches your layout. Height is coded in the prefix: a VQFN is very thin and a WQFN thinner still, following JEDEC thickness classes, so a WQFN and a QFN of the same pin count share a footprint but differ in profile. Pin density is the second axis — multi-row and advanced QFN (aQFN, DRQFN, MRQFN) add interior rows of terminals to reach I/O counts approaching a chip-scale BGA while keeping a leadframe’s lower cost, as NASA’s NEPP survey documents. Die attach is the third: most QFNs are wire-bonded, but a flip-chip QFN bumps the die onto the leadframe for better RF performance.
The fourth axis is singulation, which quietly constrains the rest. A sawn QFN is molded in a large array and cut apart, while a punch type is molded in individual cavities; both are JEDEC-compliant per NXP’s AN1902, but only the sawn process readily supports the wettable-flank options below.
Wettable-flank QFN: the automotive variant
Standard QFN terminals end flush at the package edge as bare, oxidation-prone copper, so after reflow there is no reliable side fillet, and automated optical inspection cannot confirm the joint. On ordinary QFNs, sidewall solder coverage varies from 50 percent to 90 percent, per TI, which forces expensive X-ray or full electrical test to catch defects.
A wettable-flank package fixes this by exposing and tin-plating a side flank so a visible solder fillet forms. The two accepted methods, per TI’s plating brief, are a step-cut leadframe and a dimple leadframe; Amkor identifies step-cut as the mainstream solution for pitches at or below 1.0 mm, where saw burrs otherwise spoil the flank. AOI vendors target a solder fillet height of at least 0.10 mm for reliable detection, and Allegro’s wettable-flank layout extends the terminal land to about 1.00 mm (40 mil) to accommodate it.
For sourcing, the feature shows up in the part number. TI marks wettable-flank logic with a W in the orderable code and an AEC-Q100 qualification, so a WQFN with the modification reads with that suffix on the datasheet. If a leadless part is going into an automotive board inspected by AOI, a wettable flank is effectively mandatory.
[IMAGE 2: cross-section of a step-cut wettable-flank terminal forming a side solder fillet versus a plain QFN flank | alt: “Wettable-flank QFN step-cut terminal forming a side solder fillet for AOI”]
Standards and layout: IPC-7093, the exposed pad, and voiding
Two standards govern QFN design. JEDEC defines the outlines — MO-220 for QFN, MO-229 and MO-241 for DFN and SON — while IPC-7093, Design and Assembly Process Implementation for Bottom Termination Components, covers the land pattern, stencil, and reliability rules shared across the family. Suppliers deviate from the JEDEC nominal, so the datasheet land recommendation always wins over a generic outline.
The exposed pad is where designs go wrong. It carries most of the heat and often the ground, so it must be via-stitched to internal planes; a well-designed QFN reaches a junction-to-board resistance near 3 to 5 degrees C per watt on a four-layer board. The assembly risk is solder voiding under that pad, which IPC-A-610 limits to 25 percent of the area for production acceptance. Controlling it is a stencil problem: split the pad aperture into a grid at roughly 50 to 70 percent paste coverage, and keep aperture openings off the via locations so paste is not wicked away.
How to decode a QFN part number and choose a variant
Start by resolving the name. Match the datasheet’s package label against the cross-reference above: LFCSP, MLF, MLP, LPCC, LLP, and HVQFN are QFNs; SON is a DFN; a height prefix like V or W only changes thickness. That tells you the footprint family before you read a dimension.
Then pick the variant from the application. For a low-I/O power or analog part, a DFN saves space. For high I/O in a small body, a multi-row QFN beats a single-row part. For anything automotive inspected optically, require a wettable flank and an AEC-Q grade. Confirm the pitch against your fabricator, since 0.4 mm QFN demands tighter tolerances than 0.5 mm, and, for high-shock or thermal-cycling service, plan for underfill, which suppliers recommend to improve QFN board-level reliability.
Design mistakes and failure modes
The recurring QFN failures start at the exposed pad and the flanks.
Leaving the thermal pad floating, or bonding it to solid copper with no thermal vias, throws away the heat path that justified the package. Ignoring the 25 percent void limit lets a large single void disconnect the vias from the die and spike thermal resistance. Specifying a plain QFN for an AOI-inspected automotive board guarantees inspection escapes, since the joint cannot be seen, and a wettable flank is the fix. On the fine-pitch small parts, uneven paste or pad design causes tombstoning and bridging, and because the joints are hidden, these survive to the field unless caught by X-ray. Each is a layout or sourcing decision, not a fab defect.
FAQ
What is the difference between QFN and DFN?
Both are leadless packages with an exposed thermal pad, but a QFN has terminals on all four sides of the body while a DFN has them on only two opposing sides. DFN, also called SON, suits low-pin-count parts like power-management and sensor ICs. QFN handles higher pin counts. JEDEC outlines them separately as MO-220 and MO-229.
Is LFCSP the same as a QFN?
Yes. LFCSP (Lead Frame Chip Scale Package) is Analog Devices’ brand name for a standard QFN. Electrically and mechanically it is a leadless quad package with perimeter pads and a central exposed pad, and it follows the same JEDEC MO-220 construction. Other names for the same package include MLF, MLP, LPCC, and LLP.
What is a wettable-flank QFN?
It is a QFN whose side terminals are step-cut or dimpled and tin-plated so a visible solder fillet forms on the package edge after reflow. Ordinary QFN flanks are bare copper that oxidizes and gives 50 to 90 percent inconsistent side coverage, which optical inspection cannot verify. Wettable flanks enable AOI, which is why automotive parts use them.
What is MLF or MicroLeadFrame?
MicroLeadFrame, abbreviated MLF, is Amkor’s trademarked name for its QFN and DFN packages. It describes the same leadless, copper-leadframe, exposed-pad construction as a generic QFN, with no functional difference. onsemi uses MLP for the equivalent. Treat all of these as QFN or DFN when reading a datasheet or building a footprint.
What is the exposed pad on a QFN for?
The exposed pad is a metal area on the package underside connected to the die-attach paddle. It provides the main thermal path from the die into the PCB copper and usually a ground connection. It must be soldered to a matching PCB land that is via-stitched to internal planes; leaving it unconnected loses most of the package’s heat dissipation.
Does a QFN need underfill?
Not for typical consumer use, but suppliers recommend underfill for high-reliability, automotive, and high-shock applications. It improves thermal-cycle performance and mechanical robustness by distributing stress across the joints rather than concentrating it at the small solder connections. For benign environments, a properly designed and voided joint is sufficient without underfill.
What to do
Decode the name first: LFCSP, MLF, MLP, LPCC, LLP, and HVQFN are QFNs, SON is a DFN, and a V or W prefix only changes height, so identify the footprint family before touching a dimension. Choose the variant from the load: DFN for low pin count, multi-row QFN for high I/O in a small body, and a wettable-flank AEC-Q part for anything inspected by AOI. Design the exposed pad as a real connection with a via array, hold voiding under 25 percent with a split stencil aperture, and confirm the 0.4 or 0.5 mm pitch against your fabricator before layout. When the environment is harsh, add underfill.
