A chip scale package (CSP) is a single-die IC package whose footprint is no larger than 1.2 times the silicon die it contains. That size rule, set by IPC/JEDEC J-STD-012, is what separates a CSP from an ordinary surface-mount package. This guide defines the CSP, breaks down the five construction types you meet in real datasheets, and gives the numbers you need to choose between a CSP, a QFN, and a BGA.
| Key takeawaysA package qualifies as a CSP when its area is ≤ 1.2× the die area and it is a single-die, directly surface-mountable part (IPC/JEDEC J-STD-012).Five construction families exist: wafer-level (WL-CSP), flip-chip (FCCSP), leadframe (LFCSP), rigid-substrate, and flexible-substrate CSP.WL-CSP is the most common CSP in phones and wearables — essentially the bumped die with a redistribution layer and no substrate.Most WL-CSPs ship at moisture sensitivity level 1 (MSL1) per J-STD-020, so no pre-bake is needed before reflow (per Renesas WLCSP guidelines).The part is often cheaper than a QFN or BGA, but the 0.3–0.5 mm pitch can push the PCB into HDI territory — weigh system cost, not package cost. |
What is a chip scale package (CSP)?
A chip scale package is a single-die semiconductor package with an area no greater than 1.2 times the die area, built for direct surface mounting. The 1.2× ceiling comes from IPC/JEDEC standard J-STD-012. A ball pitch of 1 mm or finer is a second criterion the industry commonly applies.
The idea dates to 1993, proposed by Junichi Kasai of Fujitsu and Gen Murakami of Hitachi Cable, with the first demonstration credited to Mitsubishi Electric. Wafer-level versions reached volume production in the early 2000s, led by assembly houses such as ASE. The goal was constant: shrink the package until it is barely bigger than the silicon, then connect it straight to the board through a solder-ball array instead of leads and bond wires.
Vendors brand the same idea under different names. You see DSBGA (Texas Instruments), UCSP (Maxim), MicroSMD (National Semiconductor), and MicroCSP (Analog Devices) on datasheets that all describe a wafer-level CSP. Recognizing these as the same underlying package saves time during part selection.
[IMAGE 1: cross-section comparison of WL-CSP, FCCSP and LFCSP construction | alt: “Cross-section diagram comparing WLCSP, FCCSP and LFCSP chip scale package construction”]
The five types of chip scale package
JEDEC-aligned references classify CSPs by how the die connects to the outside world. Five construction families cover essentially every commercial part.
Wafer-level CSP (WL-CSP) builds the interconnect on the wafer before dicing. A copper redistribution layer (RDL) routes the die’s peripheral pads to a bump grid, and solder balls are formed directly on the die surface. There is no substrate and no bond wire, so the finished package equals the die size.
Flip-chip CSP (FCCSP) mounts the die face-down on a thin organic substrate, usually bismaleimide triazine (BT), using copper-pillar or solder bumps. The substrate fans the die’s fine 40–100 µm pad pitch out to a board-friendly 0.3–0.5 mm, and it carries more routing layers than a WL-CSP’s thin RDL (per JLCPCB’s CSP guide).
Leadframe CSP (LFCSP) uses a conventional etched leadframe with solderable lands instead of leads. Amkor’s MicroLeadFrame (MLF) is the well-known example; the same construction is sold as a quad-flat no-lead (QFN) part.
Rigid-substrate CSP attaches the die to a small ceramic or laminate interposer, wire-bonded or flip-chip bonded, then overmolded. The interposer is only fractionally larger than the die.
Flexible-substrate CSP uses a flex circuit as the interposer, which decouples some thermomechanical stress between die and board.
| CSP type | Construction | Typical ball pitch | Where it appears |
| WL-CSP | RDL and solder balls formed on the wafer; no substrate or bond wire | 0.3–0.5 mm | PMICs, sensors, RF front-ends in phones and wearables |
| FCCSP | Die flip-mounted face-down on a thin BT organic substrate | 0.3–0.5 mm | SoCs and processors needing more routing or I/O |
| LFCSP | Etched leadframe with solderable lands (Amkor MLF / QFN) | 0.4–0.8 mm | Converters, amplifiers, general-purpose analog |
| Rigid-substrate CSP | Die on a small ceramic or laminate interposer, overmolded | ≤ 1.0 mm | Memory and mixed-signal devices |
| Flexible-substrate CSP | Die on a flex-circuit interposer that relieves stress | ≤ 1.0 mm | Stress-sensitive or curved-surface assemblies |
WLCSP: the CSP you will actually meet
For most engineers, “CSP” in practice means WL-CSP — the format that dominates power-management, sensor, and RF parts in consumer electronics. Its structure is worth knowing because it drives your layout.
Below the solder ball sits a polymer stress-buffer film, typically polyimide or PBO, that absorbs thermomechanical strain during thermal cycling. Under that, the copper RDL carries signals from the original bond pads to the bump positions — a single RDL layer for simple parts, dual-layer for denser routing. Because every step happens at wafer level, cost scales with wafer area rather than per-package assembly time, which is why WL-CSP undercuts an equivalent QFN or BGA at small die sizes and high volume.
A fan-in versus fan-out distinction is worth flagging. Classic fan-in WL-CSP keeps all balls within the die outline, so the package stays at die size and meets the 1.2× rule. Fan-out wafer-level packaging (FOWLP) reconstitutes diced dies in a molded wafer and places balls beyond the die edge; it buys more I/O but often exceeds the 1.2× ceiling, so purists treat it as a related technology rather than a true CSP.
The size payoff is concrete. Nordic’s nRF52832 SoC ships as a 6 × 6 mm QFN48 and as a 3.0 × 3.2 mm WL-CSP — the wafer-level part occupies under 30% of the QFN’s board area (per Nordic Semiconductor). WL-CSP assembly is also widely available: foundries including TSMC and GlobalFoundries offer it in house.
[IMAGE 2: WL-CSP beside a QFN package for scale on a coin | alt: “Wafer-level chip scale package next to a QFN package showing relative footprint size”]
CSP vs BGA vs QFN: the comparison that matters
Choosing a package is a system decision, not just a size contest. The table below sets the CSP formats against the two packages they most often replace.
| Parameter | WL-CSP | FCCSP | QFN | Standard BGA |
| Footprint vs die | ≤ 1.2× (≈ die size) | Slightly larger (substrate) | ~2–5× die | Larger, substrate-based |
| Typical pitch | 0.3–0.5 mm | 0.3–0.5 mm | 0.4–0.8 mm | 0.5–1.0 mm (FBGA <0.5) |
| I/O sweet spot | Tens to ~200 | Hundreds+ | ≤ ~100 | 100s–1000s |
| Thermal path | Balls only; limited >~500 mW | Substrate ± lid | Exposed pad; best >1 W | Balls ± thermal balls |
| PCB required | HDI / via-in-pad at 0.4 mm | Standard–HDI | Standard SMT | Standard–HDI by pitch |
| Reworkable | Yes (hot air; fragile die) | Yes | Yes (easiest) | Yes |
| Drop robustness | Good standoff; no underfill (fan-in) | Often needs underfill | Robust | Underfill for handhelds |
| Relative unit cost | Low (small die, high volume) | Higher | Low | Higher |
A few rules of thumb fall out of the data. A QFN’s exposed center pad is a dedicated low-resistance heat path, which matters for parts dissipating more than about 1 W; a WL-CSP spreads heat across its balls with no thermal pad and becomes limiting above roughly 500 mW (per JLCPCB). On routing, an 0.8 mm BGA pitch escapes on a standard 4-layer board with 100 µm trace and space, while a 0.4 mm WL-CSP typically forces via-in-pad and HDI construction — the package gets cheaper, the board gets more expensive.
A selection decision path
Work the problem in this order:
- Size or cost forcing a bare-die footprint? If the enclosure demands the smallest possible part and volume is high with a small die, start with WL-CSP.
- More than ~200 I/O or high routing complexity? Move to FCCSP or a fine-pitch BGA; the substrate gives routing layers a thin RDL cannot.
- Dissipating more than ~1 W? A QFN with an exposed pad, or a BGA with thermal balls, manages heat a WL-CSP cannot.
- Contract manufacturer limited to standard SMT? A QFN at 0.5–0.8 mm pitch is the path of least resistance; reserve 0.3–0.4 mm CSP for lines with fine-stencil and fine-placement capability.
As a single-line heuristic from current practice: a ~200 mW Bluetooth SoC is a natural WL-CSP candidate, while a 1 W applications processor is not.
Design, assembly, and reliability
CSPs reward attention to a handful of process details that never appear on the datasheet’s front page.
Solder paste. At 0.3–0.5 mm pitch, standard Type 3 paste is too coarse. Specify Type 4 or Type 5 no-clean paste, whose 25–36 µm spheres release cleanly from fine stencil apertures and resist bridging (per JLCPCB).
PCB and escape routing. Fine-pitch CSPs generally require via-in-pad — filled and plated — plus HDI layer counts. Budget for that during quoting, not after the first fabrication run.
Moisture handling. Most WL-CSPs qualify at MSL1 per IPC/JEDEC J-STD-020, meaning no pre-bake is required before assembly (per Renesas). Still confirm the level on the specific datasheet, because larger arrays can carry a higher MSL.
Board-level reliability. Mechanical drop performance is characterized to JEDEC JESD22-B111: a 1500 g peak, 0.5 ms half-sine pulse applied package-down, with failure defined as 100 Ω for 200 ns recorded three times across five consecutive drops (per NXP application note AN3846). The 2016 revision, JESD22-B111A, tightened the test board from 132 × 77 mm to 77 × 77 mm and from 8 to 10 layers, and added pad and solder-mask specs for 0.4 mm pitch. Thermal-cycle life is characterized to JESD22-A104 over −40 °C to +125 °C, with roughly 1000 cycles targeted for arrays up to 6 × 6 mm and 500 cycles above that (per Maxim application note AN1891). The outline itself follows JEDEC MO-211 for die-size fine-pitch BGAs.
Underfill. Fan-in WL-CSPs usually skip underfill because the polymer buffer and tall solder standoff absorb strain. FCCSPs and parts headed for drop-prone handhelds or harsh automotive environments often need underfill to stop solder-joint cracking from CTE mismatch (per JLCPCB and RayPCB).
Rework. CSP rework mirrors BGA practice — hot air from top and bottom, a correctly sized nozzle, controlled reflow. One published profile applies top and bottom heaters for 30 s at 300 °C and 150 °C respectively (per NXP AN3846). A removed and replaced part has already seen extra reflows and sits near its qualified survivability limit.
Compliance and lifecycle
CSPs carry the same regulatory obligations as any other component. Expect RoHS and REACH declarations, and for automotive designs, AEC-Q100 qualification at the required temperature grade. MSL and floor-life handling per J-STD-020 apply from the moment the dry-pack is opened.
Second-sourcing is the weaker point. A WL-CSP is intimately tied to one die and one bump map, so a drop-in alternate is rare; plan for a single source or a substantially different footprint on any backup part. Confirm lifecycle status early — wafer-level parts tied to a specific process node can reach end-of-life when the node does.
Frequently asked questions
What is the difference between a CSP and a BGA?
A BGA is any package with a solder-ball array under a substrate; a CSP is defined by size — its area must be within 1.2× of the die (J-STD-012). Many CSPs are ball-grid parts, but a large BGA whose body far exceeds the die is not a CSP. “CSP” describes how small the package is, while “BGA” describes how it connects.
Is a WLCSP the same as a flip chip?
They overlap but are not identical. A WL-CSP is a finished, testable package with solder balls formed on the wafer and a redistribution layer inside. “Flip chip” describes the face-down mounting method and can also mean a bare bumped die attached directly to a substrate. Historically some vendors used the terms interchangeably; today WL-CSP implies the packaged, RDL-bearing part.
Can you hand-solder a chip scale package?
Rarely, and not reliably. At 0.3–0.5 mm pitch with balls hidden under the die, CSPs need stencil-printed paste, controlled reflow, and often via-in-pad boards. Prototyping is possible with a hot-air station and a stencil, but production demands SMT reflow and X-ray inspection of the joints.
What is the maximum size for a chip scale package?
The package area must not exceed 1.2 times the die area, per IPC/JEDEC J-STD-012, and the part must be a single die that mounts directly to the board. A ball pitch of 1 mm or finer is a common additional requirement. Anything larger than the 1.2× ratio is classed as a fine-pitch BGA or another package type, not a CSP.
Does a WLCSP need underfill?
Usually not. Fan-in WL-CSPs rely on a polymer stress buffer and a relatively tall solder standoff to absorb thermal strain, so most consumer parts ship without underfill. Underfill becomes worthwhile for drop-sensitive handhelds, large arrays, or automotive-grade reliability, where it guards against solder-joint cracking from CTE mismatch.
What moisture sensitivity level is a WLCSP?
Most WL-CSPs are rated MSL1 under IPC/JEDEC J-STD-020, so they tolerate unlimited floor life at factory conditions and need no pre-bake before reflow (per Renesas). Larger or more complex parts can carry a higher level, so verify the MSL printed on the specific datasheet before setting handling rules.
The bottom line
Choose a chip scale package when board area is the binding constraint and your volume, die size, and assembly line can support a 0.3–0.5 mm pitch. Default to WL-CSP for small, low-power analog, sensor, and RF parts; step up to FCCSP or a fine-pitch BGA once I/O count or power exceeds what a bare-die footprint carries; and stay with a QFN when you need a simple SMT process or an exposed thermal pad above 1 W. Whichever you pick, price the whole system — the CSP that saves a few cents on the part can add dollars to the PCB.
