A PSOP package is one of two unrelated things. Amkor’s Power Small Outline Package is a wide-body SOIC with a copper heat slug under the die, sold as PSOP-2 and PSOP-3. Intel’s Plastic Small Outline Package is a 44-lead flash memory package with no exposed pad at all. Confusing them costs a board spin, so this page separates them, then gives the dimensions, thermal numbers and land pattern for the power version.
[IMAGE 1: side-by-side bottom views of a PSOP-2 with a flush heat slug and a PSOP-3 with a protruding slug, slug dimensions called out | alt: “PSOP package bottom view comparing PSOP-2 flush heat slug and PSOP-3 protruding exposed pad”]
Key takeaways
- PSOP has two expansions. Power SOP has a heat slug; Plastic SOP does not. Resolve the acronym to a case-outline drawing before you route anything.
- The 28-lead Power SOP is dimensionally a wide-body SOIC to JEDEC MS-013-AE, with a 13.45 mm to 13.70 mm by 4.55 mm to 4.80 mm slug added underneath.
- PSOP-2 has a flush slug; PSOP-3 has an enlarged slug that protrudes, so it can be soldered to board copper.
- Slug down and soldered to 3 in² of copper, a 28 PSOP-2 measures 33.4 °C/W in still air against 52 °C/W for the package alone.
- Thermal via array: 0.30 mm to 0.33 mm diameter on a 1.2 mm grid, tented, with the stencil aperture 0.25 mm smaller than the copper pad.
- Do not print 100% paste on the thermal land. A single full-area aperture floats the part and opens the perimeter joints.
What PSOP means: two packages, one acronym
PSOP expands to either Power Small Outline Package or Plastic Small Outline Package. The power version is a thermally enhanced SOIC with a copper slug that the die sits on, developed by Amkor. The plastic version is Intel’s 44-lead flash memory package on a 1.27 mm pitch with no thermal feature. Both appear in distributor taxonomies under the same three letters.
| Power SOP (PSOP-2, PSOP-3) | Plastic SOP (Intel PSOP) | |
| Expansion | Power Small Outline Package | Plastic Small Outline Package |
| Originator | Amkor Technology | Intel flash memory SOP family |
| Exposed pad | Yes — copper heat slug under the die | None |
| Typical lead count | 20, 24, 28 | 44 |
| Lead pitch | 1.27 mm | 1.27 mm (50 mil) |
| Typical outline | Wide-body SOIC, 17.90 mm × 7.50 mm at 28 leads | 28.2 mm × 16 mm |
| Typical devices | xDSL line drivers, switching regulators, audio amplifiers | 2 Mb to 8 Mb flash, x8 or x16 |
| Why it was chosen | Power dissipation | Board area against 32-lead PLCC, and lead inspection |
Table 1. The two packages that share the PSOP acronym. Power SOP data from the Amkor description and the Analog Devices RP-28 outline; Plastic SOP data from Intel’s Small Outline Package family brief.
One consequence matters for sourcing. A line item that says only “PSOP” is not a specification. Resolve it to a manufacturer case-outline number before quoting: the two families share no footprint, lead count or thermal path.
Power SOP dimensions and the heat slug
The 28-lead Power SOP is a standard wide-body SOIC outline with a slug added. Analog Devices publishes it as RP-28 and states compliance with JEDEC MS-013-AE, which is why the perimeter land pattern is the same one you would draw for any 28-lead SOIC-300.
| Dimension | Value (mm) |
| Body length, D | 17.90 BSC |
| Body width, E1 | 7.50 BSC |
| Lead span, E | 10.30 BSC |
| Overall height, A | 2.35 – 2.65 |
| Standoff, A1 | 0.10 – 0.30 |
| Lead width, b | 0.31 – 0.51 |
| Lead thickness, c | 0.20 – 0.33 |
| Foot length, L | 0.40 – 1.27 |
| Lead pitch, e | 1.27 BSC |
| Lead angle | 0° – 8° |
| Heat slug, bottom | 13.45 – 13.70 × 4.55 – 4.80 |
Table 2. 28-lead Power SOP outline per the Analog Devices RP-28 drawing, compliant to JEDEC MS-013-AE.
The slug is large relative to the body. At roughly 13.6 mm by 4.7 mm it covers most of the die shadow, and Amkor’s original 28 PSOP-2 slug is quoted at 535 mils by 170 mils, which converts to 13.6 mm by 4.3 mm. Two slug sizes in the same family are worth checking against the specific case drawing rather than assuming.
Standoff is the other variable. The Amkor part shipped in two lead forms, a 9 mil normal standoff and a 2 mil low standoff, the low version intended for direct slug attachment. A footprint drawn for one and populated with the other will not reflow the same way.
PSOP-2 vs PSOP-3, slug up vs slug down
PSOP-2 carries a standard exposed slug flush with the package bottom. PSOP-3 carries an enlarged slug that protrudes below the body so it makes solid contact with board copper. The distinction sounds cosmetic and is not: it decides which direction the heat leaves.
The same package also ships in two mounting orientations. Slug down puts the slug against the PCB, soldered to a copper area, and needs the low standoff lead form. Slug up turns the die over and leaves the slug facing ambient, where an external heat sink can be epoxy bonded or clipped to it.
Pick slug down when the board can carry the heat and the assembly must stay automated. Pick slug up only when a real heat sink is available and dissipation exceeds what copper alone takes, which the numbers below put near 2 W.
Thermal performance: what the slug actually buys
Renesas publishes measured data for the 28 PSOP-2 across mounting and cooling combinations, taken with a 100 mil by 100 mil thermal die. This table is the most useful thermal data published on this package and it appears on none of the pages currently ranking for it.
| Mounting condition | Ambient condition | θ (°C/W) |
| Slug up, package alone | Still air | 52 |
| Slug up + Wakefield 8052-60 heat sink | Still air | 25 |
| Slug up + Wakefield 8052-60 heat sink | 100 LFM | 12.9 |
| Slug up + Wakefield 8052-60 heat sink | 200 LFM | 11 |
| Slug up + Wakefield Penguin 658-60AB | 600 LFM | 7.7 |
| Slug down, soldered to 3 in² copper | Still air | 33.4 |
| Slug down, soldered to 3 in² copper | 100 LFM | 30 |
Table 3. Measured thermal resistance for the 28 PSOP-2, from Renesas application note AN1096 (Elantec EL75XX), thermal die 100 mil × 100 mil.
Read the table as a decision, not a spec. Soldering the slug to a large copper area takes the package from 52 °C/W to 33.4 °C/W, which supports about 2 W. Adding airflow to a slug-down board barely helps, moving only to 30 °C/W at 100 LFM, because the board is now the bottleneck. A bonded heat sink with the slug facing up is what unlocks the 7 W to 9 W range.
The interface material matters there. Renesas lists case-to-heat-sink resistance from 0.14 °C/W for a 6 W/mK elastomer pad to 1.1 °C/W for a 0.74 W/mK compound — an eightfold spread in series with everything else.
A worked example from the other end. Analog Devices characterizes the AD8016ARP in a 20-lead PSOP-3 at 18 °C/W when soldered to a 10 in² plane of 1 oz copper, which lets it dissipate 3 W at 70 °C ambient against a 125 °C junction limit. Junction-to-case for that part is 0.86 °C/W, so essentially the entire thermal budget is board, not package. The same die in the SO-Batwing package is rated for meaningfully less power under identical conditions.
For scale: a plain 8-lead SOIC runs near 95 °C/W and a SOT-23-5 near 240 °C/W. The slug is worth a factor of three to five, and the copper attached to it is worth as much again.
Land pattern, thermal vias and stencil
The perimeter pads follow ordinary SOIC rules: NXP puts pad width at about 60% of the lead pitch, extended 0.5 mm past the foot at heel and toe.
| Feature | Recommendation |
| Lead pad width at 1.27 mm pitch | 0.60 mm |
| Pad extension beyond the foot | 0.5 mm at heel and toe |
| Thermal land area | At least the size and shape of the exposed pad |
| Clearance, thermal land to lead pads | ≥ 0.25 mm |
| Thermal via diameter | 0.30 – 0.33 mm, 1 oz copper barrel plating |
| Thermal via grid pitch | 1.2 mm |
| Solder mask tenting over vias | Mask diameter ≥ 0.1 mm larger than the via |
| Segmented thermal land | Matrix pads 1.0 – 2.0 mm, gaps 0.2 – 0.4 mm |
| Stencil thickness at 1.27 mm pitch | 0.125 – 0.150 mm |
| Thermal land stencil aperture | 0.25 mm smaller than the copper pad, segmented |
| Paste coverage on the thermal land | 50% – 80% of the land area |
| Gap between stencil segments | ≥ 0.15 mm |
Table 4. Exposed-pad SOIC land pattern, via and stencil recommendations, from NXP application note AN2409 rev 3.0.
Two of those numbers cause most of the defects. Printing a single full-area aperture puts down so much paste that the molten pool lifts the package and opens the perimeter joints, which is why the aperture is reduced and segmented. And an unplugged via in the thermal land wicks solder down the barrel during reflow, dropping standoff and leaving voids in the joint you cannot see.
Set an X-ray void limit and hold it. IPC-A-610 is commonly applied at 25% maximum voiding in the thermal pad, and pSemi states that figure explicitly in its exposed-pad assembly guidance. Voids in the thermal path are the difference between the datasheet number and the board you actually built.
Check the board stackup before trusting any θJA. NXP’s worked example for a 32-lead wide SOIC shows 79 °C/W on a single-layer JEDEC board against 27 °C/W on a four-layer 2s2p board, same package. Most of what a datasheet calls package performance is board performance.
[IMAGE 2: PSOP land pattern drawing showing perimeter pads, segmented thermal land, 1.2 mm via grid and the 0.25 mm clearance | alt: “PSOP package land pattern with segmented thermal land and 1.2 mm thermal via grid”]
Naming decoder: the same package under other names
Every supplier renamed this idea. If a second source is needed, search on the construction rather than the acronym.
| Name | Supplier usage | What it is |
| PSOP-2, PSOP-3 | Amkor, Analog Devices, Elantec/Renesas | Wide SOIC with copper heat slug, flush or protruding |
| SOICW-EP, HT-SOICW-EP, eSOICW-EP | NXP / Freescale | Wide SOIC with exposed die pad; HT denotes low-thermal-resistance die attach |
| SOIC-PowerPAD (DDA and similar) | Texas Instruments | SOIC with exposed thermal pad |
| HSOP | Multiple suppliers | Heat-sink SOP, generic name for the same construction |
| HTSSOP | Texas Instruments and others | TSSOP with exposed pad, 0.65 mm pitch |
| HVSSOP / MSOP-PowerPAD | Texas Instruments | MSOP with exposed pad; TI and industry names for one package |
| TSSOP-EP | Analog Devices and others | TSSOP with exposed pad |
Table 5. Names used for a small outline package with an exposed thermal pad, from supplier package documentation and application notes.
Handling, compliance and failure modes
- Moisture. Wide-body SOIC packages in this family are classified MSL 3, giving 168 hours of floor life at 30 °C and 60% RH with a 260 °C peak package temperature. Bake per J-STD-033 if the dry pack has been open longer.
- Placement accuracy. An exposed pad does not self-align strongly during reflow, so a package that would have pulled itself straight as a plain SOIC will stay where the machine put it.
- Electrical state of the slug. On some parts the pad is isolated; on others it sits at the die substrate potential. Read the datasheet before tying it to a plane — an isolated pad and a substrate pad want different copper.
- Cleaning. Standoff under the body is small, so water-soluble flux and aqueous cleaning are poor choices; Amkor recommends against them for low-clearance thermal packages.
- Rework. Bake at 125 °C for 16 to 24 hours before removing a part, and do not exceed the original reflow peak or ramp rates when putting the replacement down.
- Solder mask over the heat path. Analog Devices lists this explicitly among its thermal design mistakes: do not run solder mask over copper that is doing the heat sinking.
Is PSOP still a live package
As a name, it is fading. Suppliers largely moved to their own designations, and the construction now appears as exposed-pad SOIC, HSOP or PowerPAD in current catalogs. The acronym survives in distributor package filters — Mouser still lists a PSOP-8 package category for power management ICs — and in legacy BOMs.
That creates a specific sourcing risk. A cross-reference tool matching on the string “PSOP” can return a Plastic SOP flash memory against a Power SOP line driver. Match on case-outline drawing number, lead count, body dimensions and the presence of an exposed pad, in that order.
For new designs, treat Power SOP as a construction rather than a part to specify. Choose the current supplier package with the thermal performance you need and draw the land pattern from its case drawing.
[IMAGE 3: cross-section of an exposed-pad SOIC on a board showing heat flow from die through slug, solder joint, thermal vias and into inner-layer copper | alt: “PSOP exposed pad heat flow cross-section through thermal vias into PCB copper”]
Frequently asked questions
What does PSOP stand for?
Either Power Small Outline Package or Plastic Small Outline Package, depending on the supplier. The power version is a wide SOIC with a copper heat slug under the die. The plastic version is Intel’s 44-lead flash memory package with no exposed pad. Check the case-outline drawing to tell which one a document means.
Is a PSOP the same as a SOIC?
Mechanically the Power SOP is a wide-body SOIC. The 28-lead version follows JEDEC MS-013-AE, so the perimeter pads are identical to a 28-lead SOIC-300 footprint. The difference is a copper slug on the bottom that needs its own thermal land, via array and stencil treatment.
What is the difference between PSOP-2 and PSOP-3?
PSOP-2 has a standard exposed slug flush with the package bottom. PSOP-3 has a larger slug that protrudes below the body so it seats against board copper for better heat transfer. PSOP-3 is the choice when the exposed pad will be soldered to a PCB plane.
Do I have to solder the exposed pad?
For the rated thermal performance, yes. Manufacturer thermal figures assume the pad is soldered to a copper plane; leaving it unsoldered costs a substantial fraction of the improvement. On an Analog Devices exposed-pad part, the soldered and unsoldered figures differ by roughly a quarter.
Should the PSOP thermal pad connect to ground?
Only if the datasheet says so. Some exposed pads are electrically isolated from the die and can go to any convenient plane; others sit at the substrate potential, often the negative supply. Tying a substrate pad to ground shorts the part.
What should I use instead of PSOP in a new design?
The same construction under a current name: an exposed-pad SOIC, HSOP, or a PowerPAD SOIC if the footprint is flexible. For lower power in less area, an HTSSOP or HVSSOP with an exposed pad covers most of the range that Power SOP once served.
What to do next
Start by resolving the acronym. Find the case-outline drawing for the exact part number, confirm whether an exposed pad is present, and record its dimensions.
Then design the thermal path rather than the package. Draw the thermal land to the pad size, put 0.30 mm vias on a 1.2 mm grid into inner-layer copper, tent them, segment the stencil to 50% to 80% coverage, and set an X-ray void limit at 25%. If the calculation still fails, the answer is more copper or a slug-up mount with a bonded heat sink, in that order — airflow over a slug-down board buys almost nothing.
