HTSSOP-14 is a 14-lead, 0.65 mm-pitch TSSOP body with an exposed thermal pad added to the underside, marketed by Texas Instruments as PWP0014A. The pad drops junction-to-ambient thermal resistance well below a standard TSSOP-14 or SOIC-14, but only if the PCB land pattern, stencil, and via design match the datasheet — get the footprint wrong and the pad does nothing.
Key takeaways
- TI’s 14-pin PowerPAD outline is drawing PWP0014A (mechanical drawing 4214867/A, revised 09/2016), rated to 1.2 mm max package height.
- Lead pitch is 0.65 mm across 14 leads (7 per side), each 0.30/0.19 mm wide — identical to standard TSSOP-14.
- Footprint area for HTSSOP-14 (PWP) runs 22 mm² (4.4 × 5 mm), against 52 mm² (8.65 × 6 mm) for SOIC-14 — a 58% smaller board footprint for the same pin count.
- The exposed pad is not automatically ground — check the pin table; some devices tie it internally to ground and still require an external ground connection, others use it purely as a thermal path.
- Real 14-pin PowerPAD thermal data (DRV81004-Q1, JEDEC 2S2P board): RθJA 43°C/W, RθJC(top) 44.5°C/W, RθJB 21°C/W — figures assume 2 W dissipation, 70°C ambient.
- Solder stencil aperture size for the pad scales with stencil thickness: TI publishes four combinations from 0.175 mm stencil / 2.67×2.75 mm opening down to 0.1 mm stencil / 3.53×3.64 mm opening.
Land pattern and mechanical dimensions
The PWP0014A drawing defines the HTSSOP-14 mechanical envelope: 14 leads at 0.65 mm pitch, lead width 0.30 mm max / 0.19 mm min, package height capped at 1.2 mm. This is the same lead geometry as a standard 14-pin TSSOP — the pad is the only addition.
| Parameter | Value | Source |
| Lead count / pitch | 14 leads, 0.65 mm pitch (7 per side) | TI PWP0014A drawing 4214867/A |
| Lead width | 0.30 mm max / 0.19 mm min | TI PWP0014A drawing 4214867/A |
| Max package height | 1.2 mm | TI PWP0014A drawing 4214867/A |
| Body footprint (PWP-14) | 22 mm² (4.4 × 5 mm) | TI THS3115 datasheet |
| Body footprint (SOIC-14, comparison) | 52 mm² (8.65 × 6 mm) | TI THS3115 datasheet |
| Base JEDEC family | MO-153 (TSSOP outline family) | Analog Devices RU-14 drawing |
Don’t copy pad dimensions from a generic HTSSOP-14 reference for a new design — the maximum exposed pad size and PCB land should always come from the specific device’s datasheet, since pad size varies by part within the PWP0014A envelope.
Stencil design by thickness
TI’s PWP0014A package documentation gives four stencil-thickness/aperture-opening pairs for the thermal pad, letting a board house pick based on their process capability rather than guessing:
| Stencil thickness | Solder stencil opening |
| 0.175 mm | 2.67 × 2.75 mm |
| 0.15 mm | 2.88 × 2.97 mm |
| 0.125 mm (reference design) | 3.155 × 3.255 mm |
| 0.1 mm | 3.53 × 3.64 mm |
The pattern holds across TI’s thermally-enhanced packages: thinner stencil, larger aperture, to keep paste volume consistent. Diodes Inc.’s TSSOP-14 land pattern documentation notes that a more robust pattern for wave soldering is calculated by adding 0.2 mm to the Z dimension, and points to IPC-7351A for the underlying land pattern naming convention — worth checking against your own reflow vs. wave process before finalizing gerbers.
General via and coverage rules from TI’s PowerPAD application report still apply at this pin count: via diameter of 0.33 mm (13 mils) or smaller with 1 oz. copper plating, five to nine vias for a small die, and a minimum 50% solder joint coverage of the pad area (typical processes hit over 80% without special optimization).
Thermal performance: real 14-pin numbers
TI’s DRV81004-Q1, a 4-channel automotive low-side driver in the 14-pin PWP0014L HTSSOP, publishes a full thermal table: RθJA (junction-to-ambient) of 43°C/W, RθJC(top) of 44.5°C/W, RθJB (junction-to-board) of 21°C/W, ψJT of 3.6°C/W, ψJB of 20.9°C/W, and RθJC(bottom) of 10.1°C/W. These figures assume a JEDEC-defined 2S2P board, 2 W power dissipation, and 70°C ambient temperature — treat them as comparison numbers, not a guarantee for your board, since actual θJA shifts with copper area and via count as covered above.
| Thermal metric | Value | Test condition |
| RθJA (junction-to-ambient) | 43 °C/W | JEDEC 2S2P board, 2 W, 70°C ambient |
| RθJC(top) (junction-to-case, top) | 44.5 °C/W | Same as above |
| RθJB (junction-to-board) | 21 °C/W | Same as above |
| ψJT (junction-to-top characterization) | 3.6 °C/W | Same as above |
| ψJB (junction-to-board characterization) | 20.9 °C/W | Same as above |
| RθJC(bottom) (junction-to-case, bottom/pad) | 10.1 °C/W | Same as above |
For a broader comparison point, TI’s DRV8434A datasheet shows an HTSSOP RθJA of 29.7°C/W against 39°C/W for the equivalent VQFN package on a JEDEC standard 4-layer PCB — a reminder that HTSSOP and QFN thermal pads don’t perform identically even at similar pin counts, and the datasheet’s own number for your specific part beats any generic package-family estimate.
Is the thermal pad connected to ground?
Not always — check the pin table for your specific device. TI’s TPS54383/TPS54386, a 14-pin HTSSOP dual synchronous buck converter, lists the ground pin as “connect directly to Thermal Pad,” making the pad an active ground node, not just a passive heat path. TI’s TPS1HTC30-Q1, also a 14-pin HTSSOP automotive smart switch, describes its pad as “internally shorted to ground” while still instructing the designer to tie it to IC ground externally — internal shorting doesn’t remove the external connection requirement. Never assume pad function from the package alone; a floating pad on a device that expects it grounded, or a grounded pad on a device that expects electrical isolation, both cause real failures.
TSSOP-14 vs. HTSSOP-14
| Attribute | TSSOP-14 | HTSSOP-14 (PWP0014A) |
| Lead pitch | 0.65 mm | 0.65 mm (same) |
| Lead count | 14 | 14 (same) |
| Exposed thermal pad | No | Yes, underside |
| Max package height | ~1 mm (standard TSSOP) | 1.2 mm |
| PCB attach for rated thermal performance | Leads only | Leads + soldered pad |
| Typical use case | Low-power logic, general ICs | Power switches, buck converters, motor/relay drivers |
If your device’s standard-package power dissipation already clears your worst-case load at your operating ambient, plain TSSOP-14 saves the extra land-pattern and via work — HTSSOP-14 earns its keep specifically when the datasheet’s thermal derating curve is the constraint.
Sourcing reality
Real 14-pin HTSSOP automotive and power parts carry meaningful unit cost at low volume: TI’s TPS1H100BQPWPRQ1, a 14-HTSSOP N-channel power switch, lists at $2.20 per unit on DigiKey, with several sibling parts in the same 14-HTSSOP family — TPS1H100AQPWPRQ1, TPS1HTC100QPWPRQ1, TPS1HC100BQPWPRQ1 — all confirmed in the same 14-HTSSOP package by DigiKey’s own part descriptions. Check part-status flags (active vs. NRND vs. obsolete) before locking a BOM line, the same as with any package family.
Frequently asked questions
What is the land pattern for HTSSOP-14?
TI’s PWP0014A drawing (4214867/A) defines 14 leads at 0.65 mm pitch, 0.30/0.19 mm lead width, 1.2 mm max height, with the thermal pad’s solder-mask-defined size and stencil aperture varying by device — always confirm against the specific part’s datasheet.
What stencil thickness should I use for HTSSOP-14?
TI publishes four working combinations: 0.175 mm stencil with a 2.67×2.75 mm aperture, down to 0.1 mm stencil with a 3.53×3.64 mm aperture — pick based on your board house’s process capability.
Is the HTSSOP-14 thermal pad always ground?
No. Some devices (TPS54383/86) tie the pad directly to the ground pin; others (TPS1HTC30-Q1) internally short it to ground but still require an external tie. Always check the specific pin table.
How much smaller is HTSSOP-14 than SOIC-14?
Roughly 58% smaller footprint — 22 mm² (4.4×5 mm) versus 52 mm² (8.65×6 mm) for SOIC-14, per TI’s THS3115 datasheet.
What via size should I use under an HTSSOP-14 pad?
0.33 mm (13 mil) diameter or smaller with 1 oz. copper plating, five to nine vias for a small die, non-thermal-relief construction.
The decision
Design to HTSSOP-14 (PWP0014A) when your device’s standard-package thermal derating curve can’t cover your worst-case dissipation and board area still matters more than a QFN’s slightly better RθJA — expect roughly 22 mm² of body footprint, a 0.65 mm lead pitch identical to plain TSSOP-14, and a pad whose ground/thermal function you must confirm per part, not per package family. Pull the stencil aperture and via pattern from the specific datasheet before sending gerbers; the PWP0014A envelope is consistent, but pad size and stencil recommendation are not.
[IMAGE 1: PWP0014A land pattern with dimensioned pad and lead pitch | alt: “HTSSOP-14 PWP0014A land pattern diagram”]
[IMAGE 2: Solder stencil aperture comparison at four stencil thicknesses | alt: “HTSSOP-14 stencil aperture by thickness table”]
[INTERNAL LINK: HTSSOP package overview and thermal design → HTSSOP package guide]
[INTERNAL LINK: PCB thermal via design for exposed-pad packages → PCB layout guide]
[INTERNAL LINK: How to read JEDEC thermal resistance specs → thermal metrics guide]
