When a design has a Z-height budget, IC package height decides which parts fit — and the datasheet often hides the answer behind a single letter. JEDEC assigns profile codes where T means thin (1.00–1.20 mm) and V means very thin (0.80–1.00 mm). This guide maps those codes to real millimeters, sorts packages by height against their thermal penalty, and gives a decision path for height-constrained boards.
Key takeaways
- Package height is “seated height” — the max above the board — not body thickness alone.
- JEDEC 30F defines the bands: L low (1.20–1.70 mm), T thin (1.00–1.20 mm), V very thin (0.80–1.00 mm), U ultra-thin (0.50–0.65 mm).
- A TSSOP tops out at 1.20 mm versus 1.75 mm for SOIC and 1.00 mm for a low-profile QFN (TI qfncompare data).
- Going thinner costs heat: a QFN-16 sits near 38.7 °C/W θJA while the same-function TSSOP-16 is 108 °C/W (TI, JESD51-5).
- WLCSP/DSBGA reach roughly 0.5 mm total thickness — the thinnest practical option (Analog Devices AN-617).
- Below ~0.8 mm, warpage and standoff become the real constraints, not the datasheet height number.
What “package height” actually means
Datasheets specify height as the A dimension — the maximum seated height from the PCB surface to the top of the package. That is not the same as the molded-body thickness, and it is not the mounted height once you add a heatsink or clearance.
For leaded parts, seated height includes the standoff (A1) plus the body. For a QFN it is almost all body, since standoff is near zero. For a BGA or WLCSP, height is the body plus the collapsed solder ball. Always design your Z-budget against the datasheet max, not the nominal, and add the ball or standoff where the part has one.
Worked example. Suppose an enclosure gives you 1.30 mm of clearance above the board. A TSSOP at 1.20 mm max height leaves only 0.10 mm — too little once you add solder-paste height and board flatness tolerance. A 1.00 mm QFN leaves 0.30 mm, a safer margin. Subtract the package max height from clearance, then subtract paste (~0.10–0.15 mm) and coplanarity before you call it a fit.
The JEDEC profile-height code letters
Package names encode height in a prefix letter defined by JEDEC standard JESD30 (30F). Once you know the letters, a name like TSSOP or TVSOP tells you the height band before you open the drawing.
What does low profile mean in an IC package? Under JEDEC 30F, “low profile” (code L) means a seated height above 1.20 mm and up to 1.70 mm. “Thin” (T) is 1.00–1.20 mm, “very thin” (V) is 0.80–1.00 mm, and progressively thinner codes run down to fractions of a millimeter.
| JEDEC code | Profile name | Seated-height band |
| (blank) | Standard | >1.70 mm to 2.45 mm |
| L | Low | >1.20 mm to 1.70 mm |
| T | Thin | >1.00 mm to 1.20 mm |
| V | Very thin | >0.80 mm to 1.00 mm |
| W | Very, very thin | >0.65 mm to 0.80 mm |
| U | Ultra thin | >0.50 mm to 0.65 mm |
| X | Extremely thin | 0.50 mm |
| X1 | Extra-thin | >0.40 mm to 0.50 mm |
| X2 | Super-thin | >0.30 mm to 0.40 mm |
Source: JEDEC JESD30F profile-height codes, reproduced in TI SSZU002.
This is why LQFP (the L is “low profile”) is 1.40 mm, and TQFP (thin) drops to 1.00–1.20 mm — the letter is the spec. Both are registered together under JEDEC outline MS-026, so the profile letter, not a separate drawing, is what distinguishes them. The same logic applies across families: read the leading letter, then confirm the A dimension in the drawing.
The leaded low-profile ladder: SOIC to TVSOP
Among gull-wing leaded packages, height drops in a predictable ladder as the family shrinks. Standard SOIC has a 1.75 mm max height at 1.27 mm pitch. SSOP tightens pitch to 0.65 mm but can actually run taller, up to 2.00 mm in some 14/16-pin bodies (TI qfncompare tables).
TSSOP is the workhorse thin option: 1.20 mm max height at 0.65 mm pitch, with JEDEC body widths of 3.0, 4.4, and 6.1 mm. Below it, TVSOP (thin very-small-outline, TI designator DGV) reaches the same 1.20 mm max at a finer 0.40 mm pitch, trading routing difficulty for footprint. The height plateau for leaded parts is around 1.00–1.20 mm — to go lower, you leave leads behind.
Going below 1 mm: QFN, WLCSP, and X-thin codes
Leadless packages break the 1 mm barrier. A low-profile QFN reaches 1.00 mm max height, and thinner QFN variants drop into the very-thin and ultra-thin bands. Because a QFN has essentially no standoff, its seated height is nearly all usable silicon and mold.
The floor is wafer-level packaging. WLCSP (also called DSBGA) is a package the size of the die itself, with total assembled thickness around 0.5 mm and available bump pitches of 0.5, 0.4, 0.35, and 0.3 mm (Analog Devices AN-617; TI AN-1112). Bumped-die height starts near 0.3 mm minimum before the board-side ball. If your budget is under 0.8 mm, WLCSP is usually the only path — at the cost of X-ray inspection and fragile handling.
IC package height comparison
| Package (14/16-pin) | Max height | Profile code | Pitch | θJA (JESD51-5) |
| SOIC (D) | 1.75 mm | (standard) | 1.27 mm | ~57–73 °C/W |
| SSOP (DB) | 2.00 mm | (standard) | 0.50–0.65 mm | ~69–82 °C/W |
| TSSOP (PW) | 1.20 mm | T (thin) | 0.50–0.65 mm | ~83–108 °C/W |
| TVSOP (DGV) | 1.20 mm | T (thin) | 0.40 mm | ~92–120 °C/W |
| QFN (RGY) | 1.00 mm | T / V | 0.50 mm | ~37–39 °C/W |
| WLCSP / DSBGA | ~0.5 mm | X (extremely thin) | 0.3–0.5 mm | die-dependent |
Heights and θJA from TI qfncompare tables (JESD51-5, high-K board); WLCSP thickness from Analog Devices AN-617 and TI AN-1112.
[IMAGE 1: side-view height ladder of SOIC, TSSOP, QFN, WLCSP drawn to scale with mm labels | alt: “IC package height comparison side view from 1.75 mm SOIC to 0.5 mm WLCSP”]
The thermal cost of thin
Thinner is not free. As you drop height and mass, the package’s ability to spread heat falls, and junction-to-ambient thermal resistance climbs. In TI’s logic comparison on the same board, a 16-pin SOIC sits near 73 °C/W while the 16-pin TSSOP rises to about 108 °C/W and TVSOP to roughly 120 °C/W.
The exception is the QFN. Its exposed thermal pad routes heat straight into the board, so despite being one of the thinnest leaded-alternative options at 1.00 mm, the QFN-16 lands near 38.7 °C/W — better than a SOIC three times its height. If you need both thin and cool, a QFN with a well-designed thermal pad beats a leaded thin package. If you go WLCSP, plan the board copper as the heatsink, since the package has almost no thermal mass.
The height reduction also cuts mass and lead parasitics, which helps signal integrity even as it hurts heat spreading. In TI’s 16-pin data, average lead inductance falls from about 3.45 nH for SOIC to 2.59 nH for TSSOP and 0.82 nH for QFN, and package mass drops from ~0.15 g (SOIC) to ~0.036 g (QFN). Thin leadless parts win on parasitics; they lose on the thermal mass that a taller body provides.
A height-budget decision path
Work from your Z-clearance down:
- Budget ≥ 1.75 mm → SOIC is fine; easiest to hand-solder and inspect.
- Budget 1.20–1.70 mm → move to a low-profile (L) part such as LQFP (1.40 mm), or TSSOP for two-sided parts.
- Budget 1.00–1.20 mm → thin (T) TSSOP/TQFP; watch θJA rising past 100 °C/W on high-pin counts.
- Budget 0.80–1.00 mm → very-thin (V) QFN; use the exposed pad for both height and thermal wins.
- Budget < 0.80 mm → WLCSP/DSBGA at ~0.5 mm; accept X-ray inspection, tighter escape routing, and warpage risk.
Ultra-thin risks: warpage, MSL, standoff
Below roughly 0.8 mm, the datasheet height stops being the hard constraint. Thin, low-mass packages warp more during reflow, and coplanarity across a fine-pitch WLCSP array becomes the yield-limiter, not the nominal thickness.
Two more items belong on the checklist. Thin packages often carry a stricter MSL (moisture sensitivity level) rating, so bake before reflow if floor life is exceeded. And remember the mounted height adds the solder ball or standoff — a 0.5 mm WLCSP body plus its ball is taller on the board than the body number alone. Design the enclosure to the assembled stack-up, verified on a real cross-section, not the package drawing.
Frequently asked questions
How tall is a TSSOP package?
A TSSOP has a maximum seated height of 1.20 mm, which puts it in JEDEC’s “thin” (T) profile band of 1.00–1.20 mm. That is roughly a third shorter than a standard SOIC at 1.75 mm, which is why TSSOP is the default choice when both footprint and height are constrained.
What is the thinnest IC package?
Wafer-level chip-scale packages (WLCSP, also called DSBGA) are the thinnest practical option, with total assembled thickness around 0.5 mm and bumped-die heights starting near 0.3 mm. They fall in JEDEC’s “extremely thin” (X) band and are the package the size of the die itself.
What does low profile mean in a package?
Under JEDEC JESD30, “low profile” is the code L: a maximum seated height above 1.20 mm and up to 1.70 mm. LQFP (the L stands for low profile) is the common example at 1.40 mm. “Thin” (T), “very thin” (V), and “ultra-thin” (U) are progressively shorter bands.
How thin is a QFN package?
A low-profile QFN reaches a 1.00 mm maximum height, and thinner variants drop into the very-thin (0.80–1.00 mm) band. Because a QFN has almost no standoff, nearly all of that height is usable, and its exposed pad keeps thermal resistance low despite the thin body.
Does a thinner package run hotter?
Usually yes for leaded parts: less mass means higher junction-to-ambient thermal resistance. A 16-pin TSSOP is near 108 °C/W versus about 73 °C/W for SOIC (TI, JESD51-5). QFN is the exception — its exposed pad drops θJA near 38 °C/W despite the thin body.
Bottom line
Read the profile letter first: L, T, V, and U tell you the height band before you open the drawing. Size the package to your Z-budget from the top of the ladder down, and stop at the first family that fits — SOIC if you have 1.75 mm, TSSOP at 1.20 mm, QFN at 1.00 mm with a thermal-pad bonus, WLCSP only when you are under 0.80 mm. Then verify the assembled stack-up, budget for the higher θJA of thin leaded parts, and confirm MSL and warpage margins before release.
