An HTSSOP (Heat-sink/thermally-enhanced Thin Shrink Small Outline Package) is a standard TSSOP body with an exposed metal pad added to the underside for direct PCB heat conduction. Texas Instruments markets its version as PowerPAD (PWP); other vendors use their own suffixes for the same JEDEC outline. The pad turns a package rated for under a watt into one that can handle several watts, provided the board is laid out to use it.
Key takeaways
- HTSSOP = TSSOP body + exposed thermal pad on the underside, soldered to a PCB thermal land.
- Same body widths as TSSOP (3.0, 4.4, 6.1 mm) and the same 0.5/0.65 mm lead pitch — the pad is the only geometric addition.
- Texas Instruments calls it PowerPAD (PWP); NXP’s equivalent JEDEC outline is SOT117-x; JEDEC’s own designation is MO-153.
- The pad gives a low-resistance path (θJP) from the die directly to the PCB, letting the exposed pad be reflow-soldered like any other SMT feature — no clips, grease, or external heatsink.
- Pad soldering isn’t optional: TI states the package should not be used without the exposed pad soldered to the board, or thermal and mechanical performance both suffer.
- Thermal gain is board-dependent: soldered on a low-conductivity board, PowerPAD ran 73% cooler than an unsoldered standard package; on identical boards, 44% cooler on average.
HTSSOP vs. TSSOP vs. SOIC
TSSOP is a rectangular surface-mount plastic IC package with gull-wing leads, smaller and thinner than SOIC or TSOP at the same lead count, suited to mounted heights under 1 mm. Body widths run 3.0, 4.4, and 6.1 mm with lead counts from 8 to 80 and lead pitch of 0.5 or 0.65 mm. HTSSOP is that same body with a pad added.
| Attribute | SOIC | TSSOP | HTSSOP |
| Lead pitch | 1.27 mm | 0.65 mm (0.5 mm on some variants) | Same as TSSOP |
| Typical body width | 3.9–10.3 mm | 3.0 / 4.4 / 6.1 mm | Same as TSSOP |
| Mounted height | ~1.75 mm | ≤1 mm | ≤1 mm |
| Exposed thermal pad | No (standard) | No | Yes, underside |
| Board attach for full rating | Leads only | Leads only | Leads + pad soldered |
| Typical θJA improvement, same board | — | Baseline | ~44% lower |
Naming cross-reference
Buyers get tripped up here more than on any other spec, because every vendor renamed the same JEDEC outline:
- Texas Instruments: PowerPAD, part-number suffix PWP
- JEDEC standard designation: MO-153, JEDEC’s name for the HTSSOP-28
- NXP: SOT117-2 for the HTSSOP-28
- ROHM: HTSSOP-Bxx (e.g., HTSSOP-B20)
- Generic/other vendors: often just “HTSSOP” or “TSSOP with exposed pad”
When cross-referencing a second source, match the JEDEC MO-153 (or the pin-count-specific JEDEC outline) rather than the vendor suffix — PWP and SOT117-2 parts from different vendors can be pin-and-thermal-pad compatible even though the datasheet uses different terminology.
Thermal performance: what the pad actually buys you
Thermal resistance is the temperature drop from the packaged die to its primary heat sink per watt dissipated, denoted θJx. For HTSSOP the relevant figures are θJA (junction-to-ambient) and θJP (junction-to-pad).
Two real datasheet examples show the range in practice:
- A 20-pin HTSSOP (PWP) motor-driver package is specified at 1.4°C/W θJC to handle dual high-current drivers in that space.
- A 20-pin HTSSOP (PWP) LDO regulator lists θJA figures of 37.9 and 43°C/W depending on board construction — a reminder that θJA is not a package-only constant, it depends on the PCB.
Worked example, from TI’s own comparative data
Table 1 of TI’s PowerPAD application report shows a standard 20-pin SSOP handling 0.75 W before hitting a 150°C junction at 80°C ambient, versus 3.25 W for the PowerPAD version of the same pin count — roughly a 4x increase in usable power dissipation from adding and soldering the pad. A 24-pin TSSOP goes from 0.55 W (standard) to 2.32 W (PowerPAD) under the same assumptions. Those numbers assume the pad is soldered to a board built with a proper thermal land and vias — skip that and you’re back near the standard-package number regardless of what the package outline promises.
PCB footprint and thermal via layout
The thermal land is the area of solderable copper directly beneath the package body; its solder-mask-defined pad should be sized to the maximum exposed-pad dimension given in the specific part’s datasheet, not estimated from a generic HTSSOP outline. For multilayer boards, thermal vias carry heat from the surface land down to an internal ground or power plane — check the datasheet for which plane the pad should tie to.
Practical numbers from TI’s board study:
- A via drill diameter of 0.33 mm (13 mils) or smaller works well with 1 oz. copper plating, minimizing solder wicking out of the joint during reflow.
- For small die, five to nine thermal vias is typically adequate; larger die can use more since more area is available under the package.
- Vias under the pad should use a continuous connection to internal planes rather than thermal-relief (wagon-wheel) construction, which is standard elsewhere on the board but works against heat removal here.
- TI recommends a minimum solder joint coverage of 50% of the pad area, though standard assembly processes typically achieve over 80% without special optimization.
- JEDEC’s standoff-height spec for TSSOP/TQFP runs 0.05–0.15 mm, which PowerPAD parts fall within without deviation.
HTSSOP thermal land / via checklist
| Item | Design rule |
| Pad size source | Use max exposed-pad dimension from the specific part’s datasheet |
| Via diameter | 0.33 mm (13 mil) or smaller, 1 oz. copper |
| Via count | 5–9 for small die; more for larger die/area |
| Via construction | Continuous connection to plane, no thermal relief |
| Minimum solder coverage | 50% of pad area (typical process achieves >80%) |
Assembly: reflow profile, MSL, and rework
A HTSSOP/PowerPAD part doesn’t require a different reflow profile from a standard fine-pitch SMT package — the thermal mass isn’t meaningfully increased, only the solder area at the pad. Reference numbers from the classification profile TI publishes:
| Profile stage | Sn-Pb eutectic | Pb-free |
| Preheat minimum temp | +100°C | +150°C |
| Preheat maximum temp | +150°C | +200°C |
| Time above liquidus (TL) | 60–150 s at 183°C | 60–150 s at 217°C |
| Max time 25°C to peak | 6 minutes | 8 minutes |
Rework is where HTSSOP diverges from a plain TSSOP: the exposed pad’s solder joint can’t be visually inspected — TI recommends x-ray, cross-sectioning, or electrical testing to confirm it. A documented 20-pin PowerPAD TSSOP removal profile ran at 220°C, 0.39 scfm gas flow, roughly 50 seconds preheat above board level plus a 10-second reflow step, so budget for hot-air rework tooling sized to the package rather than a standard iron.
Selecting between HTSSOP and other thermally-enhanced options
- HTSSOP vs. QFN (thermally enhanced): QFN gives a shorter, wider thermal pad and lower parasitic inductance, but no gull-wing leads to inspect visually — go QFN when board area matters more than rework-ability; go HTSSOP when you need visually inspectable leads for a low-to-mid volume board.
- HTSSOP vs. TO-220 with heatsink: TO-220 is a through-hole package built around a metal mounting tab for an external heatsink, capable of dissipating 50 W or more with an infinite heatsink — pick TO-220 when the wattage genuinely exceeds what any SMT thermal pad can carry (roughly single-digit watts), not as a default.
- HTSSOP vs. standard TSSOP: if the datasheet’s power dissipation column already covers your worst-case current draw at your ambient, don’t pay for the pad and the extra layout constraint — use plain TSSOP.
Sourcing reality
Real distributor listings underline two things engineers should check before locking a BOM to an HTSSOP part number: unit pricing at low volume is not trivial, and some HTSSOP-packaged parts do go obsolete.
- A 28-pin HTSSOP dual LDO (TPS767D325PWP) lists at $7.40 for a single unit, dropping to roughly $4.37 at 1,000-piece pricing on DigiKey.
- A 28-pin HTSSOP bipolar motor driver (DRV8824PWP) shows Part Status: Obsolete with only 7 units in stock at the time of listing — a reminder to check part-status flags before designing in an HTSSOP part, independent of the package itself.
Frequently asked questions
What does HTSSOP stand for?
Heat sink (thermally-enhanced) thin shrink small-outline package — also called thermally-enhanced shrink SOP. It’s the same JEDEC TSSOP outline with an added exposed thermal pad.
Is HTSSOP the same as PowerPAD?
PowerPAD is Texas Instruments’ name for a TSSOP with an exposed pad on the bottom; other manufacturers use the generic term HTSSOP or their own suffix for the identical JEDEC outline.
Does the HTSSOP exposed pad have to be soldered?
Yes for rated thermal performance. TI does not recommend using the package without soldering the pad to the board, citing reduced thermal performance and mechanical integrity.
What’s the difference between TSSOP and HTSSOP mechanically?
None in lead pitch or body width — only the added exposed pad on the underside and the resulting PCB land/via requirement.
What via size should I use under an HTSSOP thermal pad?
0.33 mm (13 mil) diameter or smaller with 1 oz. copper plating, non-thermal-relief construction, sized per the datasheet’s pad dimensions.
Can HTSSOP replace a QFN for thermal performance?
Often close, but QFN typically wins on board area and parasitic inductance; HTSSOP wins on lead inspectability and rework access — the deciding factor is usually assembly/rework capability, not raw θJA.
The decision
Use HTSSOP when your datasheet’s standard-package power rating falls short of your worst-case dissipation but a TO-220-class heatsink is overkill — the pad alone gets you roughly 3–4x the power handling of the same body without one, provided you commit to a proper thermal land, vias sized to 0.33 mm or less, and a soldered (not floating) pad. If you can’t verify the pad is soldered and inspected by x-ray or electrical test, don’t count on the datasheet’s enhanced number in your thermal budget.
[IMAGE 1: Bottom view of a 20-pin HTSSOP package showing the exposed thermal pad and gull-wing leads | alt: “HTSSOP package bottom view showing exposed thermal pad”]
[IMAGE 2: PCB thermal land and via pattern for an HTSSOP thermal pad | alt: “HTSSOP PCB thermal land and via layout diagram”]
[INTERNAL LINK: HTSSOP vs QFN thermal package comparison → package selection guide]
[INTERNAL LINK: How to read a JEDEC MSL rating → moisture sensitivity level guide]
[INTERNAL LINK: PCB thermal via design for exposed-pad packages → PCB layout guide]
