The PDIP package (Plastic Dual In-Line Package) is the most common and lowest-cost variant of the DIP family. It uses a molded epoxy resin body to encapsulate the IC die and lead frame, providing adequate mechanical protection and electrical insulation for commercial and industrial applications. PDIP conforms to JEDEC standards MS-001 (300 mil), MS-010 (400 mil), and MS-011 (600 mil) and remains the default through-hole IC package for prototyping, education, and legacy designs. This guide covers PDIP construction, JEDEC dimensional standards, how it compares to the ceramic alternative (CDIP), and when PDIP is still the right choice.
Key Takeaways
PDIP uses molded thermosetting epoxy resin over a copper-alloy lead frame. The body is non-hermetic—plastic is somewhat porous to moisture, so PDIP is not rated for moisture-sensitive applications requiring hermetic sealing.
Three JEDEC standards define PDIP: MS-001 for 300 mil (7.62 mm) row spacing, MS-010 for 400 mil (10.16 mm), and MS-011 for 600 mil (15.24 mm). All use 2.54 mm (100 mil) pin pitch. Pin counts range from 4 to 64.
PDIP is not hermetic. Unlike CDIP (ceramic DIP), PDIP cannot meet MIL-PRF-38535 hermetic requirements. Operating temperature is typically −40 to +85 °C (commercial grade) or −40 to +125 °C (industrial grade). CDIP extends to −55 to +175 °C (military).
PDIP costs a fraction of CDIP — roughly 1/5 to 1/20 the price for the same IC. This makes PDIP the overwhelming choice for any application that does not mandate hermeticity.
Availability is narrowing. Many IC manufacturers have moved new designs to SMD-only packages (SOIC, QFN). PDIP remains in production for legacy parts and high-volume commodity ICs (NE555, LM7805, 74HC series).
What Is a PDIP Package?
A PDIP (Plastic Dual In-Line Package) is a through-hole IC housing with two parallel rows of metal leads extending from a rectangular body molded from thermosetting epoxy resin. The IC die is bonded to a copper-alloy lead frame using conductive epoxy, wire-bonded (gold or aluminum wire) to the lead fingers, and then transfer-molded with epoxy resin at high pressure. The resin cures in under 2 minutes, enabling high-volume production.
The molding process embeds the lead frame in the plastic body, with the outer portions of the leads extending horizontally, then bent downward into the standard through-hole form. The leads are plated with tin, tin-lead, or matte tin (RoHS-compliant). Per Renesas’ PDIP package specifications, mold flash or protrusions must not exceed 0.010” (0.25 mm), and dimensions are measured with the package seated in JEDEC seating plane gauge GS-3.
[IMAGE 1: Cross-section diagram of a PDIP package showing die, lead frame, wire bonds, and epoxy mold body | alt: “PDIP package cross-section showing die lead frame wire bonds and molded epoxy body”]
PDIP Package Dimensions by JEDEC Standard
| JEDEC Standard | Row Spacing | Body Width | Max Body Height | Pin Counts | Lead Pitch |
| MS-001 | 300 mil (7.62 mm) | 6.35 mm (0.25”) | 5.33 mm (0.21”) | 4, 8, 14, 16, 18, 20, 24, 28 | 2.54 mm |
| MS-010 | 400 mil (10.16 mm) | 9.15 mm (0.36”) | 5.33 mm (0.21”) | 22 | 2.54 mm |
| MS-011 | 600 mil (15.24 mm) | 12.7 mm (0.50”) | 6.35 mm (0.25”) | 24, 28, 32, 36, 40, 48, 52, 64 | 2.54 mm |
Sources: JEDEC JEP-95 index, PCB-3D JEDEC outline reference, Renesas PDIP package specifications. Body length varies with pin count; always verify against the specific IC datasheet.
Leads are copper alloy (typically C194 or equivalent), 0.36–0.56 mm wide and 0.20–0.38 mm thick per Analog Devices N-series package drawings. Lead spacing at the tips (dimension eB) is measured with leads unconstrained; the controlling row-spacing dimension (E) is measured with leads perpendicular to the seating plane.
PDIP vs CDIP: Plastic vs Ceramic
| Property | PDIP | CDIP (CerDIP) |
| Body material | Molded epoxy resin | 92% alumina ceramic |
| Hermeticity | Non-hermetic (porous to moisture) | Hermetic (glass-frit or solder seal) |
| Thermal conductivity | ~0.2–0.5 W/m·K | ~20–25 W/m·K |
| Temperature range (typ.) | −40 to +85 °C (comm.) −40 to +125 °C (ind.) | −55 to +175 °C (military) |
| Moisture sensitivity | MSL 1–3 (per J-STD-020) | Unaffected |
| Lead material | Cu alloy, Sn or Sn/Pb plated | Kovar or Alloy 42, Au plated |
| JEDEC standards | MS-001, MS-010, MS-011 | MS-015 |
| Military qualification | Not MIL-PRF-38535 qualified | MIL-PRF-38535 QML |
| Relative cost | 1× (baseline) | 5–20× PDIP |
| Availability | Widely available | Declining; legacy only |
| Primary use | Consumer, industrial, prototyping | Military, aerospace, medical |
The footprint is interchangeable: a PDIP-16 and a CDIP-16 use the same 300 mil, 16-pin through-hole pattern, so board layouts work with either. The choice between them comes down to hermeticity requirements and operating temperature range.
PDIP Manufacturing Process
PDIP manufacturing follows a well-established sequence:
1. Die attach: The semiconductor die is bonded to the die pad of the copper-alloy lead frame using conductive epoxy (silver-filled) or eutectic solder.
2. Wire bonding: Gold or aluminum bond wires connect the die’s I/O pads to the lead fingers of the lead frame. This is done by thermosonic or thermocompression bonding at 150–200 °C.
3. Transfer molding: The wire-bonded assembly is placed in a mold cavity. Preheated epoxy resin pellets are injected under high pressure (~70 bar) and cured in under 2 minutes per Grokipedia. The mold defines the rectangular body shape and the notch (pin 1 indicator).
4. Lead forming: After demolding, the outer portions of the lead frame are trimmed and bent downward into the standard through-hole configuration. Dambar protrusions on the leads must not exceed 0.25 mm per Renesas specifications.
5. Lead plating: Leads are electroplated with tin (matte tin for RoHS) or tin-lead alloy for solderability. Marking is applied to the top surface by laser or ink.
Where PDIP Is Still Used
Prototyping and breadboarding: PDIP’s 2.54 mm pitch matches breadboard hole spacing. Every hobbyist’s first IC projects use PDIP parts.
Education: University electronics labs use PDIP ICs (74HC series, LM741, NE555) because students can hand-solder and socket them without specialized equipment.
Legacy sustaining: Industrial controllers, audio equipment, and test instruments designed with PDIP ICs in the 1980s–2000s still require drop-in replacement parts.
Low-volume production: For runs under a few hundred boards, PDIP avoids the capital cost of reflow ovens and fine-pitch stencils. Wave soldering or hand soldering is sufficient.
[IMAGE 2: Photo of assorted PDIP ICs (DIP-8, DIP-14, DIP-16, DIP-28, DIP-40) arranged by size | alt: “PDIP packages in 8 14 16 28 and 40 pin sizes showing molded plastic bodies”]
Frequently Asked Questions
What is a PDIP package?
A PDIP (Plastic Dual In-Line Package) is a through-hole IC housing with two parallel rows of leads extending from a rectangular body molded from thermosetting epoxy resin. It is the most common and cheapest DIP variant, conforming to JEDEC MS-001/010/011 standards.
What is the difference between PDIP and CDIP?
PDIP uses molded plastic (non-hermetic); CDIP uses ceramic with a hermetic glass-frit or solder seal. CDIP operates from −55 to +175 °C and meets MIL-PRF-38535 military requirements. PDIP is limited to −40 to +85/+125 °C. PDIP costs 5–20× less. The footprints are interchangeable.
Is PDIP the same as DIP?
PDIP is the plastic variant of the DIP family. “DIP” is the general term covering PDIP, CDIP, SDIP, and Skinny DIP. When a datasheet says “DIP” without qualification, it almost always means PDIP. The “P” prefix explicitly identifies the plastic body material.
Is PDIP still available?
Yes, but the range is shrinking. Major manufacturers (TI, Microchip, ON Semi, Analog Devices) still produce popular parts in PDIP (NE555, LM7805, ATmega328P, 74HC series). Many newer ICs are SMD-only. Always check production status before committing to PDIP in a new design.
Choosing PDIP — Decision Rules
Specify PDIP when cost is the priority and the application does not require hermeticity or extended temperature range. PDIP is the right choice for breadboard prototyping, low-volume production, socketed field-replaceable designs, and any legacy layout requiring a through-hole DIP footprint. For volume production, evaluate SOIC or QFN to reduce board area and assembly cost. For military or aerospace programs requiring hermeticity, specify CDIP (MS-015) instead—the footprint is identical.
