The CPGA package (Ceramic Pin Grid Array) is a hermetically sealed through-hole IC housing that places pins in a full area array across the underside of a multilayer ceramic substrate. CPGA supports pin counts from 28 to over 476 at 2.54 mm (100 mil) or 1.27 mm (50 mil) pitch, delivering the high I/O density, thermal conductivity, and hermeticity required by military processors, FPGAs, and aerospace-grade microcontrollers. This guide covers CPGA construction, JEDEC standards, how it compares to PPGA and OPGA, and when it remains the right specification.
Key Takeaways
CPGA uses a multilayer co-fired ceramic substrate (typically 90–96% alumina) with Kovar or Alloy 42 pins gold-plated and brazed to the bottom in an area array. The die cavity can be on top (cavity-up) or bottom (cavity-down, for heatsink contact).
JEDEC MS-017 defines the CPGA outline for 100 mil pitch, cavity-down configuration. Intel’s 1999 Packaging Databook documents CPGA in pin counts from 68 to 387, with staggered 100 mil pitch and Kovar over Alloy 42 leads.
CPGA weighs roughly 2× more than an equivalent PPGA or OPGA. Grokipedia documents approximately 29 g for a 296-pin CPGA versus 18 g for a 296-pin PPGA, because ceramic is denser than organic laminate.
CPGA is hermetic; PPGA and OPGA are not. For MIL-PRF-38535-qualified ICs and radiation-hardened devices, CPGA is the standard high-pin-count through-hole package.
AMD used CPGA for Socket A (462 pins, Athlon/Duron processors). Intel used CPGA for early Pentium processors before transitioning to PPGA and then FC-PGA (Socket 370).
What Is a CPGA Package?
A CPGA (Ceramic Pin Grid Array) is a square or rectangular through-hole IC package with pins arranged in a grid pattern on the underside of a ceramic substrate. The substrate is multilayer co-fired alumina ceramic, providing internal routing layers, a hermetic die cavity, and gold-metallized bonding pads. Pins are individually brazed to castellated pads on the ceramic body, then plated with gold over nickel for corrosion resistance and socket contact reliability.
The die is attached to the cavity floor using gold-tin (AuSn) eutectic or silver-glass die attach, then wire-bonded (gold wire) to the substrate metallization. The cavity is sealed with a metal lid (Kovar) using solder or seam welding, or with a ceramic lid using glass frit. Both methods provide hermetic enclosure meeting MIL-STD-883 leak rates of ≤10⁻⁸ cc He/s.
[IMAGE 1: Exploded view of a CPGA package showing ceramic substrate layers, die cavity, wire bonds, pin array, and metal lid | alt: “CPGA ceramic pin grid array package exploded view showing substrate pins and die cavity”]
CPGA Construction Variants
Cavity-Up vs Cavity-Down
In a cavity-up CPGA, the die sits in a depression on the top surface. The lid covers the die from above. Pins protrude downward. This is the traditional configuration for lower pin counts (28–132 pins), used in National Semiconductor (now TI) CPGA44, CPGA68, and CPGA84 packages per the SNOA029 application note.
In a cavity-down CPGA, the die is mounted on the pin side. The back of the ceramic substrate faces upward, allowing a heatsink to be mounted directly on the exposed ceramic or a metal heat spreader. Spectrum Semiconductor documents that “higher lead counts typically come with a cavity-down orientation for potential application of a heat sink.” This configuration is standard for pin counts above 132.
Staggered vs Non-Staggered Pin Arrays
Standard CPGA uses a 2.54 mm (100 mil) pin grid. For higher pin counts where the package cannot physically grow larger, a staggered arrangement offsets alternating rows by 1.27 mm (half the pitch). Intel’s 387-lead CPGA uses a staggered 100 mil pitch on a multilayer co-fired ceramic body with Kovar over Alloy 42 leads, per the 1999 Packaging Databook. Staggered arrays require matching ZIF sockets designed for the offset geometry.
CPGA vs PPGA vs OPGA vs LGA
| Property | CPGA | PPGA | OPGA | LGA |
| Substrate | Multilayer ceramic (90–96% Al₂O₃) | Organic laminate (BT resin) | Organic laminate | Organic or ceramic |
| Pin/pad type | Brazed Kovar pins | Press-fit or soldered pins | Soldered pins | Flat contact pads (no pins) |
| Pin pitch | 2.54 mm or 1.27 mm (staggered) | 2.54 mm | 1.27 mm typical | 0.5–1.27 mm |
| Typical pin count | 28–476+ | 296–370 | 462–1,331+ | 775–4,677+ |
| Hermeticity | Hermetic (solder/glass seal) | Non-hermetic | Non-hermetic | Non-hermetic (typ.) |
| Thermal conductivity | ~20–25 W/m·K (ceramic) | ~0.2–0.5 W/m·K (plastic) | ~0.2 W/m·K | Varies by substrate |
| Weight (296-pin) | ~29 g | ~18 g | ~18 g | N/A |
| Temperature range | −55 to +175 °C (mil) | −0 to +85 °C (comm.) | −0 to +105 °C | −40 to +100 °C (typ.) |
| Bent-pin risk | High | High | High | None (pads, not pins) |
| Socket type | ZIF PGA socket | ZIF PGA socket | ZIF PGA socket | LGA socket (spring contacts) |
| Military qualification | MIL-PRF-38535 | Not mil-qualified | Not mil-qualified | Rarely mil-qualified |
| Relative cost | 10–50× PPGA | 1× (baseline) | ~1.2× PPGA | ~1–2× PPGA |
| Key example | Intel Pentium (68–387 pin) | Intel Pentium MMX (296 pin) | AMD AM4 (1,331 pin) | Intel LGA 1700 |
Sources: Intel 1999 Packaging Databook, Intel PPGA app note 24310301, Grokipedia PGA article (weight data), Wikipedia PGA, AMD Socket A/AM4 specs.
CPGA Package Dimensions and JEDEC Standards
JEDEC MS-017 defines the Ceramic PGA outline for 100 mil pitch in cavity-down configuration. TI’s packaging portal lists 36 PGA package options, noting that “the ceramic package is hermetically sealed and is intended for high reliability for aerospace, radiation environments, and military/defense applications.”
Pin counts documented in Intel’s packaging databook: 68, 88, 132, 168, 208, 240–280, 272–320, and 387. Package footprint grows with pin count: a 68-pin CPGA is approximately 24.1 mm × 24.1 mm, while a 387-pin CPGA measures approximately 58.4 mm × 58.4 mm. Package thickness (excluding pins) ranges from 2.67 mm (0.105”) for lower counts to 2.79 mm (0.110”) for higher counts.
NXP’s SOT258-2 defines CPGA84 at 27.9 × 27.9 × 2.3 mm body dimensions with 84 pins. National Semiconductor’s SNOA029 application note documents CPGA packages from 44 to 84 pins with specific cavity-up and cavity-down outline drawings.
Where CPGA Packages Are Still Specified
Military and defense processors: MIL-PRF-38535 Class B and S microcircuits at high pin counts require hermetic packaging. CPGA is the standard through-hole solution when pin counts exceed the 40–64 range of ceramic DIP.
Radiation-hardened FPGAs: Space-grade FPGAs from Microchip (formerly Microsemi/Actel) and AMD (formerly Xilinx) are offered in CPGA for socketed installation in spacecraft avionics. Socketed mounting allows flight-spare replacement without board rework.
High-reliability ADCs and DACs: Analog Devices offers precision converters in 68-pin CPGA (package code G-68) for instrumentation and test equipment requiring hermetic protection and socket-mount field replacement.
Legacy sustaining programs: Older avionics, radar, and missile-guidance systems designed around CPGA processors in the 1990s require form-fit-function replacement parts. Rochester Electronics and other aftermarket suppliers maintain CPGA inventory.
[IMAGE 2: Photo of a CPGA-208 package from underneath showing the pin grid array, and from top showing the metal lid | alt: “CPGA ceramic pin grid array bottom pin view and top lid view”]
Handling and Bent-Pin Prevention
The single most common failure mode with any PGA package is bent pins. CPGA compounds this risk because the ceramic substrate is also brittle. If dropped onto a hard surface, both pins and substrate can be damaged. US Patent 5,064,063 documents that “a ceramic substrate is breakable” and that “modules may fracture or chip each other” during tray shipping.
Mitigation: handle CPGA devices exclusively with vacuum wands or anti-static tweezers contacting the lid only. Use JEDEC-compliant shipping trays (the Intel PPGA app note confirms CPGA and PPGA trays share external dimensions). For socketed installation, use only the designated ZIF socket lever mechanism. Never force a CPGA into a socket—if resistance is felt, inspect for pin misalignment before proceeding.
Frequently Asked Questions
What is a CPGA package?
A CPGA (Ceramic Pin Grid Array) is a hermetically sealed IC package using a multilayer ceramic substrate with pins arranged in an area array on the underside. Typical pin pitch is 2.54 mm (100 mil). Pin counts range from 28 to 476+. CPGA provides superior hermeticity and thermal performance for military, aerospace, and radiation-hardened applications.
What is the difference between CPGA and PPGA?
CPGA uses a ceramic substrate and is hermetically sealed; PPGA uses an organic/plastic substrate and is non-hermetic. CPGA weighs roughly 2× more and costs 10–50× more than PPGA. CPGA operates from −55 to +175 °C (military grade); PPGA is limited to commercial temperature ranges. Footprints may be socket-compatible.
Is CPGA the same as PGA?
CPGA is one type of PGA. PGA (Pin Grid Array) is the general family; CPGA specifies a ceramic substrate. Other PGA variants include PPGA (plastic), OPGA (organic), FC-PGA (flip-chip), and SPGA (staggered). The “C” prefix identifies the ceramic substrate material.
Why did processors move from CPGA to LGA?
LGA eliminates the fragile pins from the processor package, moving them to the socket instead. This reduces bent-pin failures during handling and allows higher pin densities at finer pitch (0.5–1.0 mm vs 2.54 mm). Intel transitioned to LGA with Socket 775 (LGA 775) in 2004. AMD followed with Socket AM5 (LGA 1718) in 2022. CPGA remains in use only for mil/aero hermetic requirements.
Specifying CPGA — Decision Rules
Specify CPGA when the design requires hermetic packaging, pin counts above 40 (where ceramic DIP maxes out), and through-hole or socketed mounting. If hermeticity is not required, OPGA or PPGA achieves the same pin count at a fraction of the cost and weight. For pin counts above 500 in new designs, evaluate ceramic column grid array (CCGA) or hermetic ceramic BGA—both provide finer pitch and better high-speed electrical performance than CPGA.
Before committing to CPGA, confirm three things: (1) the specific IC is still offered in CPGA—many manufacturers have discontinued the option, (2) a compatible ZIF socket is available and in production, and (3) your assembly process can handle the weight and fragility of the ceramic substrate. For legacy replacement, identify aftermarket suppliers (Rochester Electronics, Lansdale Semiconductor) who maintain CPGA-packaged die inventory.
