The DIP package (Dual In-Line Package) is an IC housing with two parallel rows of through-hole pins extending from a rectangular body. Invented at Fairchild Semiconductor in 1964, the DIP became the dominant IC package for three decades and remains in active use for prototyping, legacy designs, and applications requiring socketed field replacement. This guide covers every DIP variant, the JEDEC standards that define them, how they compare to modern SMD packages, and when specifying DIP still makes engineering sense.

Key Takeaways

Standard DIP pin pitch is 2.54 mm (100 mil) across all variants. Row spacing is 300 mil (7.62 mm) for up to 28 pins (JEDEC MS-001), 400 mil (10.16 mm) for 22-pin devices (MS-010), and 600 mil (15.24 mm) for 24–64 pins (MS-011).

DIP pin counts range from 4 to 64. Common counts are 8, 14, 16, 20, 24, 28 (300 mil body) and 24, 28, 32, 40, 48, 64 (600 mil body). Pins are always even. Pin 1 is marked by a notch or dot; numbering runs counterclockwise.

Four main DIP variants: PDIP (plastic, cheapest, most common), CDIP/CerDIP (ceramic, hermetic, for military), SDIP (shrink, 1.778 mm pitch), and Skinny DIP (standard pitch, narrow 300 mil body regardless of pin count).

DIP is breadboard-compatible by design. The 2.54 mm pin pitch matches standard solderless breadboard hole spacing exactly. This is not a coincidence — breadboards were designed around DIP dimensions.

DIP is increasingly legacy-only. Most new IC designs ship only in SMD packages (SOIC, QFP, QFN, BGA). Some manufacturers (Microchip, TI, Analog Devices) maintain DIP options for selected parts, but availability is narrowing.

What Is a DIP Package?

A DIP package is a rectangular electronic component housing with two parallel rows of metal pins designed for through-hole mounting on a printed circuit board. The pins extend vertically downward from the package body and insert through drilled holes in the PCB, where they are soldered on the opposite side — typically by wave soldering in production or hand soldering in prototyping.

Bryant “Buck” Rogers, Don Forbes, and Rex Rice invented the DIP at Fairchild Semiconductor in 1964. Their first design had 14 pins. The rectangular form factor was a direct response to the limited pin count of circular TO-style transistor packages, which could not accommodate the growing I/O requirements of early integrated circuits.

[IMAGE 1: Annotated DIP-14 IC showing body dimensions, pin pitch, row spacing, pin 1 notch, and counterclockwise numbering | alt: “DIP package anatomy showing pin pitch row spacing and pin 1 notch marking”]

DIP Package Variants

Variant	JEDEC Standard	Body Material	Row Spacing	Pin Pitch	Pin Count Range	Key Feature
PDIP	MS-001 (300 mil) MS-010 (400 mil) MS-011 (600 mil)	Molded epoxy plastic	300 / 400 / 600 mil	2.54 mm	4–64	Lowest cost; most common
CDIP / CerDIP	MS-015	Pressed alumina ceramic	300–900 mil	2.54 mm	8–64	Hermetic; military/aerospace
SDIP (Shrink)	Vendor-specific	Plastic	300 mil	1.778 mm (70 mil)	14–90	~40% higher pin density
Skinny DIP	MS-001 variants	Plastic	300 mil (7.62 mm)	2.54 mm	up to 28	Narrow body regardless of pin count
Windowed DIP	MS-015 with window	Ceramic + quartz window	300–600 mil	2.54 mm	24–40	UV-erasable EPROM access

Sources: JEDEC JEP-95 index, Allegro PUB26013, PCB-3D package outline reference, Wikipedia DIP article.

DIP Package Dimensions and JEDEC Standards

The three primary JEDEC standards for plastic DIP are:

MS-001: 300 mil (7.62 mm) row spacing, 6.35 mm (0.25”) body width, 2.54 mm pitch. Covers 8–28 pin PDIP. Maximum body height: 0.53 mm (0.21”) above seating plane per PCB-3D.

MS-010: 400 mil (10.16 mm) row spacing, 9.15 mm (0.36”) body width. Covers 22-pin PDIP. Same 2.54 mm pitch.

MS-011: 600 mil (15.24 mm) row spacing, 12.7 mm (0.50”) body width. Covers 24–64 pin PDIP. Maximum body height: 0.635 mm (0.25”).

Ceramic DIP (CDIP) is covered by MS-015, which extends row spacings from 300 mil to 900 mil. The Shrink DIP (SDIP) reduces the pin pitch from 2.54 mm to 1.778 mm (70 mil), achieving roughly 40% more pins per linear length than standard DIP.

Pin body dimensions: PDIP leads are copper alloy, typically 0.46–0.56 mm wide and 0.20–0.38 mm thick, plated with tin, tin-lead, or matte tin (RoHS compliant). CDIP leads are Kovar or Alloy 42, gold- or solder-dip plated.

DIP vs SOIC: When SMD Replaces Through-Hole

Property	DIP (PDIP-14)	SOIC-14 (narrow)
Mounting	Through-hole	Surface mount
Body width	6.35 mm (300 mil)	3.9 mm (150 mil)
Lead-to-lead width	~8.3 mm	~6.0 mm
Pin pitch	2.54 mm	1.27 mm
Height above board	~4.5 mm	~1.75 mm
Board area (est.)	~95 mm²	~50 mm²
PCB holes required	14 drilled holes	None
Breadboard compatible	Yes	No
Hand-solderable	Easy	Moderate
Assembly method	Wave solder / hand	Reflow oven
Typical unit cost	~1.5–3× SOIC	1× (baseline)
Availability trend	Declining	Dominant

SOIC occupies roughly half the board area of an equivalent DIP and eliminates the need for drilled holes, reducing PCB fabrication cost. For any design moving to production above a few hundred units, SOIC (or smaller QFN/QFP) is the default choice. DIP persists where breadboard compatibility, socketed field replacement, or hand-soldering accessibility is required.

PCB Layout and Assembly for DIP Packages

DIP footprints follow IPC-7251 (IPC-7253 for DIP specifically). Drill hole size should be the maximum lead cross-section plus 0.20–0.35 mm depending on producibility level. For a standard PDIP with 0.56 mm max lead width, a 0.80–0.90 mm finished hole is typical.

Annular ring minimums per IPC-2221: 0.15 mm (Class 2, general commercial) or 0.05 mm (Class 3, high reliability). Solder fillet requirements per IPC-A-610 Class 2: barrel fill ≥75%, visible fillet on component side.

Wave soldering is the standard production method for DIP. Board enters a molten solder wave (SAC305, 250–260 °C) from the bottom side. All through-hole joints form simultaneously. For mixed-technology boards with DIP and SMT, selective soldering applies solder only to the DIP joints.

Sockets: DIP ICs can be inserted into machined-pin or dual-wipe sockets rather than soldered directly. This allows field replacement without desoldering — valuable in test equipment, prototyping, and industrial controllers. ZIF (Zero Insertion Force) sockets are available for larger DIP sizes.

[IMAGE 2: DIP-28 IC in a machined-pin socket on a PCB, with soldered DIP-14 IC beside it for comparison | alt: “DIP package socketed and soldered mounting on PCB”]

Where DIP Packages Are Still Used

Prototyping and education: DIP ICs plug directly into solderless breadboards. Microchip’s ATmega328P (DIP-28) and PIC16F877A (DIP-40) remain among the most popular microcontrollers for Arduino-compatible boards and university labs.

Industrial controllers: PLCs and industrial I/O modules use socketed DIP ICs for field-replaceable logic. DIP-mounted op-amps, comparators, and timers (NE555 in DIP-8) remain standard in maintenance-accessible equipment.

Military and aerospace: CDIP packages meet MIL-PRF-38535 hermetic requirements. Legacy avionics and defense systems designed in the 1970s–1990s require DIP-compatible replacement parts.

Audio equipment: Boutique audio gear and guitar effect pedals frequently specify DIP op-amps (TL072, NE5532) and discrete logic for hand-buildability and component swapping.

Frequently Asked Questions

What does DIP stand for?

DIP stands for Dual In-Line Package. The “dual” refers to the two parallel rows of pins, and “in-line” describes the straight-line arrangement of pins along each side. It is also abbreviated DIL (Dual In-Line). The package was invented by Bryant Rogers, Don Forbes, and Rex Rice at Fairchild Semiconductor in 1964.

How do you identify pin 1 on a DIP?

Pin 1 is marked by a notch, dot, or both on one end of the package body. With the notch or dot facing up and toward you, pin 1 is at the upper left corner. Pins number counterclockwise: down the left side, across the bottom, then up the right side. Installing a DIP backward typically destroys the IC.

What is the difference between DIP and SOIC?

DIP is a through-hole package with 2.54 mm pin pitch; SOIC is a surface-mount package with 1.27 mm pitch. SOIC occupies roughly half the board area and does not require drilled holes. DIP is breadboard-compatible and easier to hand-solder. SOIC dominates modern production; DIP persists for prototyping and field-replaceable applications.

Are DIP packages still manufactured?

Yes, but the range is shrinking. Manufacturers like Microchip, TI, and Analog Devices still offer popular parts (ATmega328P, NE555, LM7805, TL072) in DIP. Many newer ICs are available only in SMD packages. For new designs, confirm DIP availability and lifecycle status before committing.

What is a DIP socket used for?

A DIP socket is a connector soldered to the PCB that accepts a DIP IC without soldering the IC itself. This allows the IC to be removed and replaced without desoldering — useful for prototyping, field repair, and testing. Machined-pin sockets provide better contact reliability than dual-wipe leaf-spring types.

Choosing DIP — When It Still Makes Sense

Specify DIP when the design requires breadboard prototyping, socketed field replacement, or compatibility with legacy board layouts. For production volumes above a few hundred units, evaluate SOIC or QFN — both reduce board area, eliminate drilling costs, and lower assembly expense. For military or aerospace programs requiring hermeticity, CDIP (MS-015) provides the same footprint with hermetic sealing.

Before finalizing a DIP selection, check three things: (1) that the specific part number is still in production in DIP — many ICs have dropped the option, (2) that your assembler supports through-hole insertion (not all SMT-focused lines have wave-solder capability), and (3) that the DIP footprint does not waste board area that could be reclaimed for routing or additional components. If all three check out, DIP remains a proven, low-risk, and immediately available choice.

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DIP Package: Dual In-Line Package Explained | fpga.io

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Image 1: “DIP package anatomy showing pin pitch row spacing and pin 1 notch marking”

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Information-Gain Data Points (Verified, Not in Top 10)

1. MS-001 max body height: 0.53 mm (0.21”) above seating plane (source: PCB-3D JEDEC outline reference)

2. MS-011 max body height: 0.635 mm (0.25”) (source: PCB-3D)

3. MS-010 covers 400 mil row spacing for 22-pin PDIP with 9.15 mm body width (source: JEDEC JEP-95 index)

4. SDIP pitch is 1.778 mm (70 mil), ~40% higher linear pin density than standard 2.54 mm (source: multiple)

5. IPC-7253 is the specific IPC-7251 sub-standard for DIP land patterns (source: IPC-7251)

6. PDIP lead width: 0.46–0.56 mm, thickness 0.20–0.38 mm (source: JEDEC MS-001 drawings)

7. Allegro PUB26013 lists PDIP under MS-001 family as OBSOLETE for new Allegro designs (source: Allegro)