The CDIP package (Ceramic Dual In-Line Package), also called CerDIP, is a hermetically sealed through-hole IC housing built from pressed alumina ceramic and closed with a glass-frit or solder seal. It provides the same footprint and pin pitch as a standard plastic DIP but delivers superior thermal conductivity, hermeticity, and temperature range—making it the required package for military, aerospace, and high-reliability applications governed by MIL-PRF-38535. This guide covers CDIP construction, JEDEC dimensions, how it compares to plastic DIP, and when it is the right choice.
Key Takeaways
CDIP uses 92% alumina (Al₂O₃) ceramic for both base and lid, pressed from a single firing. The lead frame (Kovar or Alloy 42) is embedded in lead-oxide solder glass fired at 450–470 °C to form a hermetic seal.
JEDEC MS-015 defines CDIP outlines from 300 mil (7.62 mm) to 900 mil row spacing, covering pin counts from 8 to 64. The standard 2.54 mm (100 mil) lead pitch matches PDIP, so board footprints are interchangeable.
Military ICs in CDIP are qualified under MIL-PRF-38535 and listed on the Qualified Manufacturers List (QML). Temperature grades extend to −55 °C to +175 °C for Class S (space) parts.
Windowed CDIP packages with a UV-transparent quartz or glass lid were the standard housing for EPROM devices (e.g., Intel 2716, 2764, 27256), allowing ultraviolet erasure of the floating-gate memory array.
CDIP costs 5–20× more than equivalent PDIP and is increasingly difficult to source. Many manufacturers have discontinued CDIP options except for mil/aero sustaining programs.
What Is a CDIP Package?
A CDIP package is a ceramic dual in-line package that hermetically seals an integrated circuit die inside a two-piece ceramic housing. Leads exit from both long sides in the standard DIP configuration—two parallel rows on 2.54 mm (100 mil) pitch. The defining feature is the hermetic seal: once the lid is fused to the base with glass frit, the internal cavity is impervious to moisture, ionic contaminants, and atmospheric gases. This is why CDIP is specified wherever long-term reliability under extreme conditions is non-negotiable.
[IMAGE 1: Cross-section diagram of a CDIP package showing ceramic base, die attach, wire bonds, lead frame embedded in glass frit, and ceramic lid | alt: “CDIP package cross-section showing ceramic base lid glass seal and lead frame”]
CDIP Construction and Sealing Methods
Glass-Sealed CerDIP (Frit-Sealed)
The most common CDIP variant uses lead-oxide solder glass (glass frit) to bond the ceramic lid to the base. The seal is formed at 450–470 °C (per US Patent 4,025,716). This temperature is low enough to avoid damaging most silicon dies but high enough to melt the glass into a continuous hermetic layer. The lead frame sits between base and lid, embedded in the glass, with leads protruding from both long sides.
Both base and lid are dry-pressed from 92% aluminum oxide (Al₂O₃), per TechSparks. This purity level provides excellent dielectric properties (volume resistivity > 10¹³ Ω·cm), thermal conductivity of approximately 20–25 W/m·K, and mechanical strength adequate for die-attach and wire-bond processes.
Side-Brazed Ceramic DIP
A distinct variant is the side-brazed ceramic DIP, where the lead frame is brazed to the ceramic sidewalls rather than embedded in glass. Side-brazed packages typically use gold-plated Kovar leads, provide even better hermeticity, and allow a metal (often Kovar) lid sealed by solder or seam welding. Side-brazed construction is common in multilayer co-fired ceramic packages used for high-pin-count military and space-grade ICs. It costs more than frit-sealed CerDIP.
Windowed CDIP
Windowed CDIP packages replace the opaque ceramic lid with a quartz or UV-transparent glass window. This allows ultraviolet light (typically 253.7 nm) to reach the die surface for EPROM erasure. The Intel 2716 (2 K×8-bit EPROM) and 27256 (32 K×8-bit EPROM) were classic windowed CDIP devices. The window is sealed into the lid frame with the same glass-frit process used for the standard package. In Japan, this construction is designated DIP-G (G = glass seal).
CDIP Package Dimensions and JEDEC Standards
JEDEC MS-015 defines ceramic DIP package outlines. Row spacings range from 300 mil (7.62 mm) to 900 mil, with lead pitch fixed at 2.54 mm (100 mil). The Allegro MicroSystems package designator document (PUB26013) lists CDIP under the “MS-015” family, noting it as OBSOLETE for new Allegro designs but still referenced in sustaining military programs.
| Pin Count | Row Spacing | Body Width (typ.) | Body Length (typ.) | JEDEC Standard |
| 8 | 300 mil (7.62 mm) | ≈6.35 mm | ≈10.2 mm | MS-015 |
| 14 | 300 mil (7.62 mm) | ≈6.35 mm | ≈19.3 mm | MS-015 |
| 16 | 300 mil (7.62 mm) | ≈6.35 mm | ≈19.3 mm | MS-015 |
| 20 | 300 mil (7.62 mm) | ≈6.35 mm | ≈25.4 mm | MS-015 |
| 24 | 600 mil (15.24 mm) | ≈12.7 mm | ≈31.5 mm | MS-015 |
| 28 | 600 mil (15.24 mm) | ≈12.7 mm | ≈36.0 mm | MS-015 |
| 40 | 600 mil (15.24 mm) | ≈12.7 mm | ≈52.1 mm | MS-015 |
Sources: JEDEC JEP-95 MS-015, Jotrin CERDIP-20 dimensions (25.4×6.35 mm), NXP CDIP40 package listing (600 mil). Lead pitch: 2.54 mm for all variants. Pin heights and tolerances vary by manufacturer—always verify against the specific package drawing.
CDIP vs PDIP: When Ceramic Matters
| Property | CDIP (CerDIP) | PDIP |
| Body material | 92% alumina ceramic | Molded epoxy resin |
| Seal type | Hermetic (glass frit) | Non-hermetic |
| Thermal conductivity | ≈20–25 W/m·K | ≈0.2–0.5 W/m·K |
| Operating temp. range | −55 to +175 °C (mil) | −40 to +85 °C (commercial) |
| Moisture sensitivity | Unaffected (hermetic) | MSL 1–3 (moisture-sensitive) |
| JEDEC standard | MS-015 | MS-001 / MS-010 / MS-011 |
| Lead pitch | 2.54 mm | 2.54 mm |
| Lead material | Kovar / Alloy 42, Au-plated | Cu alloy, Sn/Pb or Sn-plated |
| Relative cost | 5–20× PDIP | 1× (baseline) |
| Military qualification | MIL-PRF-38535 QML | Not mil-qualified |
| Availability trend | Declining; legacy only | Widely available |
The footprint is interchangeable: a CDIP-16 drops into the same 300 mil, 16-pin through-hole pattern as a PDIP-16. This makes mil-to-commercial downgrades (or upgrades) straightforward in PCB layout. The critical difference is hermeticity. PDIP absorbs moisture through the epoxy mold compound, which can cause popcorn cracking during reflow or degrade long-term reliability in humid environments. CDIP eliminates this failure mode entirely.
Where CDIP Packages Are Still Specified
Military and defense: MIL-PRF-38535 requires hermetic packaging for most Class B (military) and Class S (space) microcircuits. CDIP satisfies this requirement at lower cost than side-brazed multilayer ceramic packages.
Aerospace and space: Radiation-hardened ICs (e.g., BAE Systems RH1574, Microchip ATmegaS128 rad-hard MCU) are often packaged in CDIP because the ceramic and glass-seal construction withstands total-ionizing-dose (TID) environments better than plastic.
Medical implants: Hermeticity is critical for implantable electronics. CDIP or equivalent hermetic ceramic packages protect circuits from body fluids over device lifetimes exceeding 10 years.
Legacy sustaining programs: Older avionics, radar, and industrial controllers designed with CDIP ICs in the 1980s–2000s still require drop-in replacement parts. Obsolescence management firms (e.g., Rochester Electronics, Lansdale Semiconductor) supply CDIP-packaged ICs for these programs.
[IMAGE 2: Photo of a windowed CDIP EPROM (e.g., 27C256) and a standard opaque CDIP with pin-1 marking visible | alt: “Windowed and standard CDIP packages showing ceramic body and UV window”]
Sourcing and Obsolescence Realities
Most major semiconductor manufacturers have discontinued CDIP for new designs. Texas Instruments lists many CDIP parts as “NRND” (Not Recommended for New Designs) or “Obsolete.” Analog Devices and Microchip maintain selected CDIP lines for mil/aero programs. For legacy replacements, authorized aftermarket suppliers like Rochester Electronics hold last-time-buy inventory and can re-manufacture from original die.
Counterfeit risk is elevated for CDIP parts because their high unit cost and long production histories make them attractive targets for remarking. Verify authenticity through X-ray inspection, decapsulation analysis, and purchase only from OCM-authorized distributors or DLA-listed sources. SAE AS6171 test methods apply.
Frequently Asked Questions
What is a CDIP package?
A CDIP (Ceramic Dual In-Line Package) is a hermetically sealed through-hole IC package made from alumina ceramic with a glass-frit seal. It uses the same 2.54 mm lead pitch and row spacing as plastic DIP but provides superior hermeticity, thermal performance, and temperature range. CDIP is the standard package for military and aerospace ICs qualified under MIL-PRF-38535.
What is the difference between CDIP and PDIP?
CDIP uses a ceramic body with a hermetic glass seal; PDIP uses molded epoxy plastic with no hermetic seal. CDIP operates from −55 to +175 °C (military grade) versus −40 to +85 °C for commercial PDIP. CDIP costs 5–20× more. The footprints are interchangeable because both use 2.54 mm pitch on the same row spacings.
Is CDIP still used?
Yes, but almost exclusively in military, aerospace, space, and medical applications where hermeticity is mandated. Most commercial IC manufacturers have discontinued CDIP for new designs. Legacy sustaining programs source CDIP parts from aftermarket suppliers like Rochester Electronics.
What JEDEC standard covers CDIP?
JEDEC MS-015 (within JEP-95) defines ceramic DIP package outlines. It covers row spacings from 300 mil to 900 mil. Plastic DIP is covered separately under MS-001 (300 mil), MS-010 (400 mil), and MS-011 (600 mil).
Deciding on CDIP
Specify CDIP only when hermeticity is a requirement—not a preference. If the program demands MIL-PRF-38535 qualification, operates at junction temperatures above 125 °C, or must survive decades in a sealed environment, CDIP is the proven solution. For everything else, PDIP or a modern hermetic ceramic flatpack (CQFP, CLCC) offers better availability and board density.
Before committing, confirm supply: check the manufacturer’s product lifecycle status, request lead-time quotes (CDIP lead times often exceed 26 weeks), and identify at least one aftermarket second source. For new designs requiring hermeticity at higher pin counts, evaluate ceramic QFP or ceramic LGA—both offer smaller footprints and better high-speed electrical performance than DIP.
