Through-hole packages mount electronic components by inserting metal leads through drilled holes in a PCB and soldering them on the opposite side. Despite the dominance of surface-mount technology, through-hole packages remain essential wherever mechanical strength, high power dissipation, field serviceability, or breadboard prototyping drive the design. This guide covers every major through-hole package family—DIP, SIP, ZIP, TO, and PGA—with the dimensions, thermal data, and JEDEC designations you need to make a defensible package decision.

Key Takeaways

DIP is the universal through-hole IC package: 2.54 mm pitch, 4–64 pins, standardized under JEDEC MS-001 (300 mil) and MS-011 (600 mil).

TO packages handle power: the TO-92 dissipates ≤625 mW in free air, while the TO-247 reaches 150+ W with a heatsink (RθJC ≈ 0.5–1.5 °C/W depending on die size).

PGA (Pin Grid Array) supports pin counts from 68 to over 900 and remains in production at AMD for desktop processors (Socket AM5, 1,718 contacts in LGA—but earlier AM4 used 1,331-pin PGA).

Through-hole costs more per placement than SMT in volume, but delivers 3–10× higher pull strength per joint and tolerates vibration, thermal cycling, and field rework far better.

Counterfeit risk is elevated for through-hole parts because many are legacy or end-of-life. Buy from authorized distributors; verify per SAE AS6171 / AS5553.

What Through-Hole Packages Are and Why They Still Matter

A through-hole package is any component housing whose electrical leads pass through plated holes in a printed circuit board and are soldered on the opposite side, forming both a mechanical anchor and an electrical connection. Through-hole technology (THT) was the dominant assembly method from the 1960s through the late 1980s and remains the required choice for connectors, power semiconductors, transformers, electromechanical relays, and any component subjected to sustained mechanical stress or high current.

Modern mixed-technology boards commonly combine surface-mount ICs with through-hole power devices and connectors. Understanding each through-hole package family—its pin geometry, pitch, thermal path, and applicable standard—is foundational to every PCB layout and sourcing decision covered below.

[IMAGE 1: Annotated photo of a mixed-technology PCB showing DIP ICs, TO-220 regulators, through-hole connectors, and SMD passives | alt: “Mixed-technology PCB with through-hole DIP and TO-220 packages alongside surface-mount components”]

DIP — Dual In-Line Package

The dual in-line package is the most recognizable through-hole IC housing ever produced. Fairchild Semiconductor introduced it in 1964, and it became the de facto standard for logic, memory, and microcontrollers for three decades. DIP places two parallel rows of leads along the long edges of a rectangular plastic or ceramic body. Pins are numbered counterclockwise from the top-left (marked by a notch or dot). Inserting a DIP backward typically destroys the IC, so always verify pin-1 orientation before applying power.

DIP Subtypes and JEDEC Standards

PDIP (Plastic DIP) — the most common variant. Molded epoxy body. JEDEC MS-001 covers 300 mil (7.62 mm) row spacing for pin counts up to 28. JEDEC MS-010 covers 400 mil (10.16 mm) row spacing for 22-pin devices. JEDEC MS-011 covers 600 mil (15.24 mm) row spacing for 24–64 pins. The standard lead pitch across all variants is 2.54 mm (100 mil).

CDIP / CerDIP (Ceramic DIP) — JEDEC MS-015, row spacings from 300 mil to 900 mil. Glass-sealed ceramic body offering hermetic protection. Used in military (MIL-PRF-38535), space, and high-reliability applications. Significantly more expensive than PDIP.

Skinny DIP — standard 2.54 mm pitch but only 300 mil row spacing regardless of pin count, yielding a narrower body. Shrink DIP (SDIP) — reduced lead pitch of 1.778 mm (70 mil), offering roughly 40% higher linear pin density than standard DIP.

Common PDIP pin counts are 8, 14, 16, 18, 20, 24, 28 (300 mil body) and 24, 28, 32, 40, 48, 64 (600 mil body). The Motorola 68000 and Zilog Z180 represent the practical DIP ceiling at 64 pins. Modern DIP microcontrollers such as the Microchip ATmega328P (DIP-28) and PIC16F877A (DIP-40) remain in production specifically for prototyping and education.

[IMAGE 2: Side-by-side diagram of 300 mil and 600 mil PDIP packages with dimensions labeled | alt: “JEDEC PDIP package outlines showing 300 mil and 600 mil row spacing with 2.54 mm pitch”]

SIP — Single In-Line Package

A single in-line package arranges all leads in one row along one edge of the body. SIP components mount vertically on the PCB, consuming far less board area than a DIP of equal pin count. The standard lead pitch is 2.54 mm (100 mil), matching breadboard and DIP socket spacing.

SIP packages carry 2 to 23 pins and are most often used for resistor networks (e.g., Bourns 4600X series, 8-pin bussed), transistor arrays, and small hybrid modules such as DC–DC converters and optocoupler arrays. Some power SIP modules integrate a control IC, switching FET, and passive components in a single vertical package with a metal heatsink tab. Unlike DIP, SIP has no single dominant JEDEC outline—shapes vary by application and manufacturer.

ZIP — Zig-Zag In-Line Package

The zig-zag in-line package was developed in the late 1980s to increase the packing density of DRAM on memory boards. Like SIP, ZIP mounts vertically with all leads exiting from one edge—but the leads alternate left and right in a zigzag pattern. Viewed from the front, the apparent pin pitch is 1.27 mm (50 mil), but because the leads bend to opposite sides, they occupy a 2.54 mm (100 mil) grid on the PCB.

ZIP typically carried 20 or 40 pins in a body measuring roughly 3 mm × 30 mm × 10 mm (ZIP-20). The EIAJ EDR-7328 standard defines the P-ZIP outline at 1.27 mm pitch and the P-SZIP (shrink) variant at ≤0.889 mm pitch. ZIP’s commercial life was short; DRAM migrated to TSOP and SODIMM formats by the mid-1990s. Today ZIP appears only in niche analog ICs and legacy replacement stock.

TO — Transistor Outline Packages

Transistor outline packages were standardized by JEDEC for discrete semiconductors—transistors, MOSFETs, voltage regulators, SCRs, and diodes. The “TO” designation has expanded well beyond transistors. The family spans milliwatt signal devices (TO-92) to multi-hundred-watt power modules (TO-247, TO-264). Selecting the right TO package is fundamentally a thermal decision.

TO Family Thermal Comparison

Package	JEDEC Designation	Leads	RθJC Typical (°C/W)	RθJA Free Air (°C/W)	Max PD w/ Heatsink	Heatsink Mount
TO-92	TO-226	3	≈84 (varies)	≈160–200	≤625 mW (free air)	Clip-on only
TO-126	TO-225AA	3	≈5–10	≈60–80	≈10–20 W	Clip or bolt
TO-220	TO-220AB	3–7	1–3	≈50–65	≈50–100+ W	Bolt-on (M3)
TO-247	TO-247AC	3–4	≈0.5–1.5	≈30–40	100–250+ W	Bolt-on (M3)
TO-3	TO-204AA	2+case	≈0.7–1.5	≈30–40	100–250 W	Bolt-on (6-32)
TO-264	TO-264AA	3–5	0.3–0.8	≈25–35	200–300+ W	Bolt-on (M3)

Source: Analog Devices thermal resistance table (analog.com); ON Semiconductor AN1040; Infineon TO-247PLUS application note. All Rθ values are representative—consult the device datasheet for exact figures, which depend on die size and mold compound.

The TO-220 remains the workhorse power package. Its metal tab bolts to a heatsink with a standard M3 screw. Without a heatsink, a TO-220 dissipates only about 1 W safely in free air at 25 °C—the datasheet maximum assumes an infinite heatsink holding the case at 25 °C. Always derate for your actual ambient temperature using the thermal model: Tⱼ = Tₐ + (RθJC + RθCS + RθSA) × Pᵈ.

When the case (drain or collector) is at a different potential than the heatsink, an insulating washer (mica, silicone, or Kapton) is required. This adds 0.3–1.5 °C/W to the thermal path. The Infineon TO-247PLUS variant eliminates this by providing internal isolation, reducing RθJH by up to 50% versus a standard TO-247 with an isolation washer, per the Infineon application note.

[IMAGE 3: TO-92, TO-220, and TO-247 packages side by side with key dimensions annotated | alt: “TO-92 TO-220 and TO-247 through-hole power packages compared by size”]

PGA — Pin Grid Array

The pin grid array arranges leads in a full area array across the underside of a square or rectangular substrate. IBM developed the concept in the 1960s as an extension of flip-chip technology. PGA became the dominant high-pin-count through-hole package in the 1980s, when DIP’s 64-pin ceiling could no longer serve increasingly complex processors.

PGA Variants

CPGA (Ceramic PGA) — multilayer co-fired ceramic body with Kovar or Alloy 42 leads. Pin counts from 68 to 476+ at 2.54 mm (100 mil) pitch, or 1.27 mm (50 mil) staggered pitch for higher density. Intel’s 1999 packaging databook documents a 387-lead CPGA with staggered 100 mil pitch, cavity-down configuration, and a soldered metal lid. AMD used CPGA for Socket A (462-pin) Athlon and Duron processors.

OPGA (Organic PGA) — organic laminate substrate replacing ceramic. Lower cost, lighter weight, used by AMD for Socket AM2 through AM4 (AM4: 1,331 pins at 1.27 mm pitch on an organic substrate). FC-PGA (Flip-Chip PGA) — die is mounted face-down onto the substrate, placing the active surface closer to the heatsink. Intel introduced FC-PGA with the Coppermine-core Pentium III on Socket 370 in 1999 and continued through Socket G3 in 2013.

PGA components are almost never directly soldered to PCB through-holes in modern use. Instead, they insert into zero-insertion-force (ZIF) sockets that are themselves surface-mounted or through-hole-mounted to the board. This arrangement allows processor upgrades without rework. The primary risk with PGA is bent pins—a single misaligned pin can render a CPU unusable. AMD’s current desktop platform, Socket AM5, migrated to LGA (land grid array) to eliminate this failure mode, following Intel’s transition starting with LGA 775 in 2004.

Through-Hole Package Families at a Glance

Family	Lead Arrangement	Pitch	Typical Pin Count	JEDEC Standard(s)	Primary Use Case
PDIP	2 parallel rows	2.54 mm	8–64	MS-001, MS-010, MS-011	ICs: logic, MCU, op-amps
CDIP	2 parallel rows	2.54 mm	8–64	MS-015	Hi-rel / military ICs
SDIP	2 parallel rows	1.778 mm	up to 64	Vendor-specific	High-density legacy ICs
SIP	1 row (vertical)	2.54 mm	2–23	Vendor-specific	Resistor networks, modules
ZIP	1 row, zigzag	1.27 mm*	12–40	EIAJ EDR-7328	DRAM (legacy), analog ICs
TO-92	Inline, 3 leads	2.54 mm	3	TO-226	Small-signal transistors
TO-220	Tab + inline	2.54 mm	3–7	TO-220AB	Power semis, regulators
TO-247	Tab + inline	5.45 mm	3–5	TO-247AC	High-power MOSFETs, IGBTs
TO-3	2 pins + metal can	6.7 mm	2 + case	TO-204AA	Legacy power transistors
PGA	Area array	2.54/1.27 mm	68–1,331+	MS-017 (CPGA)	Processors, FPGAs

* ZIP: 1.27 mm between adjacent leads as viewed from the front; 2.54 mm effective grid on the PCB because leads alternate sides.

When to Specify Through-Hole Over Surface Mount

Through-hole is not a legacy compromise—it is the correct choice under specific, defensible conditions. Use through-hole packages when:

Mechanical stress is sustained. Connectors, switches, and board-to-wire interfaces see insertion and removal forces that shear SMT solder joints. Through-hole leads bonded through the full PCB thickness withstand 3–10× higher pull force.

Power dissipation demands a heatsink. A TO-220 or TO-247 bolted to an aluminum heatsink dissipates 50–250+ W. No SMT package of equivalent cost achieves this without custom thermal solutions.

The environment is harsh. Military (MIL-STD-810), automotive under-hood, and industrial motor-drive applications subject boards to sustained vibration and thermal cycling. Through-hole joints survive these conditions with higher reliability than equivalent SMT joints.

Prototyping or low-volume hand assembly. DIP ICs insert into breadboards and solder with a basic iron. For student labs, one-off instrumentation, and field repair, through-hole remains unmatched for accessibility.

The component simply is not available in SMT. Large electrolytic capacitors, power inductors above 100 µH / 5 A, board-mount transformers, and relays are still predominantly through-hole.

PCB Layout and Assembly Considerations

Hole diameter for through-hole leads is typically 0.1–0.3 mm larger than the lead cross-section, per IPC-2222 Class 2 guidelines. For a standard DIP lead of 0.46 mm width, a finished hole diameter of 0.8 mm is common. The annular ring—the copper pad remaining around the hole after drilling—must meet a minimum of 0.15 mm (IPC Class 2) or 0.05 mm (IPC Class 3) to ensure a reliable solder fillet.

Through-hole components occupy all PCB layers with their plated via, which reduces available routing channels on inner layers. In dense mixed-technology layouts, route high-speed SMT signals first, then place through-hole components where they do not block critical trace paths.

Wave soldering remains the primary mass-assembly method for through-hole boards. The board passes over a standing wave of molten solder (typically SAC305, Sn96.5/Ag3.0/Cu0.5, at 250–260 °C). Barrel fill of ≥75% is the IPC-A-610 Class 2 acceptance criterion. Selective soldering replaces wave for mixed-technology boards where through-hole and SMT coexist on the same side: a programmable nozzle applies solder only to through-hole joints, avoiding reflow damage to adjacent SMT components.

Obsolescence, Second-Sourcing, and Counterfeit Risks

Many through-hole IC families are mature or end-of-life. Texas Instruments, for example, lists most of its PDIP packages under Allegro’s PUB26013 classification as “OBSOLETE” for new designs—though many remain in production for sustaining demand. Before committing to a through-hole package in a new design, confirm active production status and check for a product change notification (PCN) or last-time-buy date.

Second-sourcing is strong for commodity through-hole parts. The NE555 timer (DIP-8) is manufactured by TI, STMicroelectronics, Diodes Inc., and dozens of others. For power packages, the TO-220 IRFZ44N MOSFET has equivalents from Infineon, Vishay, ON Semiconductor, and multiple Chinese suppliers.

Counterfeit risk is disproportionately high for through-hole components because their long production histories and standardized outlines make remarking easy. DIP packages are among the most frequently counterfeited IC forms per ERAI and GIDEP reports. Mitigation: source exclusively from OCM-authorized distributors (Digi-Key, Mouser, Farnell/Newark); for broker purchases, require testing per SAE AS6171 (test methods for suspect counterfeit EEE parts) and SAE AS5553 (counterfeit avoidance). X-ray fluorescence (XRF) can verify RoHS-compliant lead-free solder finishes—a common failure point for counterfeits that use legacy tin–lead plating.

[IMAGE 4: Flowchart showing through-hole package selection: start with pin count, branch to power vs signal, then to DIP/SIP/TO/PGA | alt: “Through-hole package selection decision flowchart for engineers”]

Frequently Asked Questions

What is a through-hole package?

A through-hole package is an electronic component housing with metal leads designed to pass through plated holes in a PCB and be soldered on the opposite side. Common through-hole families include DIP (dual in-line), TO (transistor outline), SIP (single in-line), ZIP (zig-zag in-line), and PGA (pin grid array). Through-hole mounting provides stronger mechanical bonds and higher power handling than surface-mount alternatives.

Is DIP through-hole or surface mount?

DIP is a through-hole package. Its leads insert through PCB holes and are soldered on the underside, typically by wave soldering or hand soldering. The surface-mount equivalent of DIP is the SOIC (Small Outline IC) or SSOP, which uses gull-wing leads soldered to pads on the PCB surface. Some vendors offer a “surface-mount DIP” footprint, but this is non-standard.

What is the difference between TO-220 and TO-247?

TO-247 is physically larger than TO-220, with a typical plastic body of 15.8 mm × 21.0 mm versus roughly 10 mm × 15 mm for TO-220. The TO-247 has a lower junction-to-case thermal resistance (0.5–1.5 °C/W vs. 1–3 °C/W for TO-220), enabling it to handle higher continuous power—commonly 150–250+ W with an adequate heatsink, versus 50–100 W for TO-220. Both use M3 bolt mounting.

Can PGA packages be soldered to a PCB?

Technically yes—PGA pins fit standard plated through-holes. Early PGA devices (Intel 486 era) were sometimes permanently soldered. In modern practice, PGA processors insert into ZIF sockets to permit upgrades and replacements. Soldering a PGA processor directly to a board is not recommended because rework requires specialized equipment, and bent-pin risk during insertion is high.

Why are through-hole parts still used instead of SMD?

Through-hole parts persist because they excel where SMT falls short: high-current connectors and power devices that need bolt-on heatsinks, mechanically stressed interfaces (USB, Ethernet jacks, relays), components that simply have no SMT equivalent (large transformers, high-value electrolytics), and educational or prototyping contexts where breadboard compatibility and hand solderability matter.

Choosing Your Package — What to Do Next

Start with the pin count and power budget. If the device needs fewer than 28 I/O and dissipates under 0.5 W, DIP or SOIC covers it—pick DIP only when you need breadboard compatibility, field replaceability via socket, or are supporting a legacy layout. For power devices up to 50 W, the TO-220 with a board-mounted heatsink is the default; above 100 W, move to TO-247 or TO-264 and budget for a chassis-mounted heatsink with thermal interface material. For pin counts above 64, PGA (socketed) or BGA (if SMT is acceptable) are the remaining options.

Confirm that the specific part number you need is still in active production in the through-hole package. Search the manufacturer’s parametric tables by package filter—many ICs that were once offered in DIP are now available only in SOIC or QFP. If the part is end-of-life, evaluate whether a socket-mounted equivalent or a drop-in SMT adapter PCB can extend the design’s production life without a full respin. For any through-hole part sourced through the broker market, require AS6171-compliant testing before accepting the lot.