A leadless package connects to the board through metallized pads or lands on the bottom of its body, not through leads that bend out the sides. JEDEC groups these as bottom termination components (BTCs), and the family includes QFN, DFN, LGA, and — loosely — CSP. They are smaller, lower-profile, and electrically faster than leaded parts, but the missing leads change everything about how you design, assemble, and inspect them. This guide covers the four types and the rules that make them work.
[IMAGE 1: underside views of a QFN (four-side pads + center thermal pad), DFN (two-side pads), LGA (land array), and WLCSP (ball array) side by side — alt: “Leadless packages compared from below: QFN, DFN, LGA, and WLCSP showing pads, lands, and balls”]
Key takeaways
- Leadless packages are bottom termination components: connections are pads or lands integral to the package body, with no protruding leads.
- QFN and DFN are leadframe-based with an exposed thermal pad; LGA uses flat lands; CSP/WLCSP is a near-die-size class that is usually ball-based.
- The exposed thermal pad is the make-or-break detail — it is the heat path and usually the ground, and IPC-7093 caps its solder voiding at 50%.
- Leadless parts do not self-center in reflow the way leaded parts do, cannot be wave-soldered, and need X-ray to verify hidden joints.
- Wettable flanks add a visible side fillet so standard AOI can inspect the joint — specify them for automotive and medical work.
What a leadless package is
A leadless package is a surface-mount package whose external connections are metallized terminals — pads or lands — that are part of the package body and sit flush on the bottom, replacing the bent leads of packages like SOIC or TSSOP. JEDEC calls this class bottom termination components (BTCs), and per NASA’s NEPP body of knowledge it covers quad flat no-lead (QFN), dual and multi-row QFN, dual flat no-lead (DFN), and land grid array (LGA).
The appeal is size and speed. With no leads, the package is close to die size, sits low on the board, and has very short connection paths, which cuts parasitic inductance and resistance and helps at high frequency. The cost is that there is no compliant lead to absorb stress or to inspect, which drives every design and process rule that follows.
The four leadless families at a glance
| Family | Terminals | Thermal pad | Typical use |
| QFN | Pads on 4 sides | Yes (exposed) | MCUs, RF, power ICs, converters |
| DFN / SON | Pads on 2 sides | Usually | Discretes, small analog, sensors |
| LGA | Land array (bottom) | Sometimes | Sensors, IMUs, modules, sockets |
| CSP / WLCSP | Solder balls (near die size) | No | High-density mobile, memory |
QFN and DFN are leadframe-based: a planar copper leadframe carries the die, and the perimeter lands are the exposed leadframe on the package bottom, per NXP’s assembly guidelines. LGA and CSP are substrate- or wafer-based. That construction split explains most of the differences — leadframe parts carry a large exposed thermal pad, while LGA and CSP generally do not.
QFN and DFN: the leadframe workhorses
QFN (Quad Flat No-lead) places pads on all four sides plus a large exposed thermal pad in the center. It complies with JEDEC outline MO-220, with bodies typically from 2 × 2 mm to 10 × 10 mm, pitches of 0.4, 0.5, or 0.65 mm, and pin counts from 4 to over 100, per distributor design data. It goes by many names — MLF (Micro Lead Frame), MLP, SON, and, at Analog Devices, LFCSP.
DFN (Dual Flat No-lead) is the two-sided sibling for low pin counts, common on discretes and small analog parts, and complies with JEDEC MO-229, per NXP’s QFN/DFN application note. Its part-number style encodes size directly: a DFN2020-6 is 2.0 × 2.0 mm with 6 I/O, per IPC conference material. QFN and DFN are not pin-compatible — the pad geometries differ — so confirm the specific footprint even when the body size matches.
Both come in punch-singulated and saw-singulated forms with slightly different edge profiles, and both are JEDEC-compliant, per NXP. The exposed pad is what sets them apart from every other leadless type, and it gets its own section below.
[IMAGE 2: cross-section of a QFN showing die, copper leadframe, wire bonds, exposed thermal pad soldered to PCB with thermal vias — alt: “QFN cross-section: die on copper leadframe, wire bonds, exposed thermal pad soldered over thermal vias”]
LGA: flat lands, sockets, and sensors
LGA (Land Grid Array) uses an array of flat metal lands on the package bottom for connection, with no leads (unlike PGA) and no balls (unlike BGA). Per NXP’s LGA application note, industry LGA sizes run from 2 × 2 mm to 27 × 27 mm with pitches from 0.4 to 1.27 mm, and land counts can reach into the thousands. A low-land-count LGA with lands only around the periphery is essentially a laminated QFN.
LGA has a split personality. Large LGAs are the classic socketed interface for processors, where the socket holds the spring contacts and the package presents only flat lands. Small LGAs are the standard body for MEMS sensors — ST’s LSM6DSO 6-axis IMU, for example, ships in a compact 14-land LGA, per ST’s product data — because the flat, low-profile lands suit shock-robust, space-constrained modules. Because LGA lands are flat, standoff is essentially zero, giving the lowest profile but leaving the least room for cleaning and the least compliant joint.
CSP and WLCSP: near-die-size, and the odd one out
CSP (Chip-Scale Package) is a size class, not a terminal style. Per IPC’s J-STD-012, a package qualifies as chip-scale when its area is no more than 1.2 times the die and it is a single-die, directly surface-mountable part, and a common additional test is a ball pitch of 1 mm or less. WLCSP (Wafer-Level CSP) builds the package directly on the wafer with a redistribution layer.
Here is the clarification the grouping hides: CSP and WLCSP are usually ball-based, so strictly they belong to the BGA family, not the truly leadless group. They earn their place alongside QFN, DFN, and LGA because they compete for the same ultra-compact designs and share the same hidden-joint inspection problem. If you need the absolute smallest footprint and can support fine-pitch reflow and X-ray, WLCSP goes smaller than any leadframe part; if you need a robust exposed thermal pad, it does not have one.
The exposed thermal pad: the make-or-break detail
For QFN and DFN, the exposed pad decides your yield. It serves two jobs at once: it is the primary heat path from the die to the PCB copper, and in most devices it is also the electrical ground (VSS), per distributor design guidance. Some power-management parts route a non-ground net through it, so always check the datasheet before tying the land to a ground plane.
The failure mode is voiding — flux gas trapped under the large pad during reflow. The controls are well defined.
| Parameter | Guideline |
| Void coverage limit | IPC-7093 caps thermal-pad voids at 50% |
| High-power target | Analog Devices recommends 90%+ solder coverage |
| RF ground limit | Voiding above 25% shifts resonance / cuts isolation several dB |
| Stencil aperture | Windowpane grid at 50–75% pad coverage |
| Stencil thickness | 0.125 mm (5 mil) at 0.5 mm pitch; 0.10 mm (4 mil) at 0.4 mm |
| Thermal vias | Plug or tent — open vias wick solder and starve the joint |
Never print a single full-size aperture over the thermal pad. A windowpane pattern vents flux and limits voids, per multiple manufacturer guides, and thermal vias should be plugged or tented so they do not wick solder out of the joint. For the perimeter, non-solder-mask-defined (NSMD) lands are preferred for reliability, while the central pad is solder-mask-defined for paste control, and an ENIG finish gives a flatter, more repeatable standoff than HASL.
Assembly reality: no self-centering, no wave solder, X-ray
Leadless parts behave differently on the line, and the differences are easy to underestimate. A leaded QFP self-centers during reflow because surface tension on the visible leads pulls the body into alignment. A QFN has no perimeter leads to grab, so it rides on the pool of solder under the thermal pad — which is exactly why too much center paste is catastrophic: the part floats, tilts, and lifts its tiny perimeter joints, per assembly references.
Two more hard constraints follow from having no protruding leads. Leadless parts cannot be wave-soldered — there is no lead for the wave to reach under the body — so they require screen-printed paste and reflow, which raises assembly cost relative to wave processes. And because the joints sit under the package, top-down visual and AOI inspection cannot see them; verifying a leadless joint requires X-ray (AXI), with dye-and-pry or cross-section for failure analysis.
Reliability and wettable flanks
The reliability concern for leadless parts is board-level reliability under thermal cycling. The root cause of solder-joint cracking is the CTE mismatch between the silicon die and the PCB: as temperature swings, the board expands more than the chip and shears the rigid, leadless joints, per QFN reliability references. A leaded package flexes its leads to absorb that strain; a leadless joint cannot, and its low standoff leaves little solder to fatigue before it cracks. For large QFNs or harsh environments, underfill or a robust land design becomes necessary.
Wettable-flank (SWF) QFN packages address the inspection half of the problem. A standard QFN has flat, non-plated terminal sides that form no side fillet, so only X-ray can confirm the joint. A wettable-flank part adds a plated surface on the terminal sidewall that forms a visible solder fillet during reflow, letting standard AOI verify the joint, per manufacturer and design references. Specify wettable flanks for automotive (AEC-Q100) and medical (IPC Class 3) work. Even without them, extending the PCB land 0.2 to 0.3 mm past the package edge encourages a solder toe that adds mechanical strength and aids inspection.
Master comparison table
| Family | Outline | Pitch | Terminals | Standoff | Inspection | Best for |
| QFN | JEDEC MO-220 | 0.4–0.65 mm | 4-side pads + EP | Very low | X-ray (AOI if SWF) | MCUs, RF, power, converters |
| DFN / SON | JEDEC MO-229 | 0.4–0.5 mm | 2-side pads | Very low | X-ray | Discretes, small analog |
| LGA | Per case outline | 0.4–1.27 mm | Land array | ~Zero | X-ray / socket | Sensors, IMUs, modules |
| CSP / WLCSP | BGA-class | 0.3–0.5 mm | Solder balls | ~Ball height | X-ray | High-density mobile, memory |
How to choose a leadless package
Work the decision in this order.
- Start from thermal and ground needs. If the part must sink heat or wants a solid ground under the die, a QFN or DFN with an exposed pad is the natural fit. Sensors and pure-signal parts often do fine on LGA or CSP without one.
- Match pin count and size. A few pins point to DFN or small QFN; higher I/O to multi-row QFN, LGA, or WLCSP; the absolute smallest footprint to WLCSP.
- Confirm your line can build it. Reflow, fine-pitch stencil printing, and X-ray are mandatory. No wave solder, and no reliable hand assembly on the thermal pad.
- Set inspection up front. If you need AOI rather than X-ray — common in automotive — require a wettable-flank variant and budget the slightly larger land.
- Check board-level reliability. For thermal cycling or shock, plan the land pattern, standoff, and any underfill early rather than after a field failure.
[IMAGE 3: decision-path flowchart from thermal/ground need through pin count, line capability, inspection, to a leadless family — alt: “Leadless package selection flowchart: thermal and ground needs, pin count, line capability, inspection method”]
Design and assembly mistakes that cause failures
- Full-coverage paste on the thermal pad. A solid aperture traps flux gas and floats the part. Use a windowpane grid at 50–75% coverage.
- Open thermal vias. Unplugged vias wick solder from the joint, starving it and degrading heat transfer. Plug or tent them.
- Assuming the exposed pad is ground. It usually is, but some parts route a signal through it. Read the datasheet before connecting to a plane.
- Skipping X-ray. You cannot confirm a leadless joint from the top. Without AXI, opens and voids ship undetected.
- Trying to hand-solder the thermal pad. An iron cannot reliably reach the belly pad; leadless parts want reflow or hot air with the right stencil.
- Specifying a standard QFN where AOI is required. Automotive and medical lines that inspect by AOI need wettable flanks; a flat-flank part will fail inspectability.
FAQ
What is a leadless package?
A leadless package is a surface-mount package that connects through metallized pads or lands on its underside rather than through protruding leads. JEDEC calls the class bottom termination components, and it includes QFN, DFN, and LGA. The packages are near die size, low-profile, and electrically fast, but their hidden joints need X-ray inspection.
What is the difference between QFN and DFN?
Both are leadframe-based leadless packages with an exposed thermal pad. QFN has pads on all four sides and scales to over 100 pins; DFN has pads on two sides for low pin counts, common on discretes and small analog parts. They are not pin-compatible, so their footprints differ even at the same body size.
What is the difference between QFN and LGA?
QFN is a leadframe package with a large exposed thermal pad and pads on the body edges. LGA is a substrate package with an array of flat lands and often no thermal pad, used for sensors, modules, and socketed processors. A low-pin-count LGA with edge-only lands is essentially a laminated QFN.
Can you hand-solder a QFN?
Not reliably. The exposed thermal pad sits under the body where a soldering iron cannot reach, so the joint and the ground connection cannot be formed by hand. QFNs need reflow or hot-air rework with a stencil that meters paste onto the pad. Perimeter pads alone are sometimes hand-touchable, but the thermal pad is not.
Why do QFN packages need X-ray inspection?
The solder joints, especially the central thermal pad, sit underneath the package where no camera can see them, so standard top-down AOI cannot confirm them. X-ray inspection reveals hidden opens, misalignment, and thermal-pad voiding. Wettable-flank QFNs add a visible side fillet that lets AOI verify the perimeter joints without X-ray.
Is a QFN a chip-scale package?
Often, yes. A QFN frequently qualifies as a chip-scale package because its outline is close to the die size, within the 1.2-times-die area that J-STD-012 uses to define CSP. But chip-scale is a size class, not a terminal style — true chip-scale parts like WLCSP are usually ball-based, while a QFN is leadframe-based with flat pads.
The bottom line
Choose a leadless package for size, low profile, and electrical speed, then respect what the missing leads take away. If the part needs to sink heat or wants a solid ground, reach for a QFN or DFN and treat the exposed pad as the critical detail — windowpane the paste, plug the vias, and keep voiding under the IPC-7093 limit. For sensors and modules, LGA gives the lowest profile; for the smallest possible footprint, WLCSP goes further but has no thermal pad. Whatever you pick, plan for reflow, X-ray, and board-level reliability from the start, and specify wettable flanks when your line inspects by AOI. The package is small; the process discipline it demands is not.
Internal links: electronic component packages (types overview) · JEDEC package outlines (MO-220/MO-229) · IC package naming conventions decoded · IPC-7351 land patterns · BGA routing and fanout.
External primary sources: NASA NEPP QFN Body of Knowledge (nasa.gov); NXP AN1902 QFN/DFN assembly guidelines (nxp.com); NXP AN2265 LGA assembly (nxp.com); STMicroelectronics LSM6DSO IMU (st.com); JEDEC MO-220 outline and IPC-7093 (jedec.org / ipc.org).
