The ZIP package is a through-hole IC package whose leads leave one edge in two staggered rows, letting a 25-lead part occupy half the board edge a straight in-line package would need. It began as a DRAM package in the late 1980s and survives today as HZIP, the heatsinked power version. The geometry has one consequence most references miss: every pin has four physical neighbors, not two.
Key takeaways
- Leads project on 1.27 mm centers viewed from the face, but land on the board in two rows on 2.54 mm centers.
- The prefix decodes: H means heatsink, S means shrunk pitch, P means plastic. The suffix on Toshiba parts is the lead pitch in millimeters.
- Toshiba’s TB6560AHQ in HZIP25 dissipates 43 W on an infinite heatsink against 4.2 W for the same die in HQFP64 on a four-layer board.
- In a zig-zag, diagonal pins are the closest pins. Toshiba defines pin 3’s adjacent pins as 1, 2, 4 and 5.
- The heat-radiating fin pins are tied to the die backside on at least one current part, so they need grounding or insulation.
Search-intent note
The bare phrase “zip package” returns file-compression results, not semiconductors. Nothing on that first page concerns integrated circuits. The winnable term for this topic is zig-zag in-line package, and this article is written to it. If you are chasing the traffic rather than the term, target that phrase plus HZIP.
What is a ZIP package?
The ZIP package, or zig-zag in-line package, is a through-hole IC package in which all leads exit one long edge of a plastic body in two staggered rows. The stagger lets adjacent leads sit closer along the edge than a single row would allow. Packages stand vertically on the board. ZIP was introduced to raise DRAM mounting density and now survives mainly in heatsinked power variants.
[IMAGE 1: side-by-side photo of a 25-lead HZIP power IC and a DIP of similar lead count, both standing on a millimeter rule, with the staggered lead rows visible | alt: “ZIP package staggered lead rows compared with a dual in-line package”]
The geometry, and what it buys
Two rows offset by 1.27 mm produce a face-on lead spacing of 1.27 mm while the holes themselves sit on 2.54 mm centers within each row. That is the whole trick: standard drilling and standard clearances, half the edge length.
Work it through on a real part. Toshiba’s TB6560AHQ is an HZIP25-P-1.27, so 25 leads at a 1.27 mm projected pitch span 24 × 1.27 mm, or 30.5 mm. Its body is 36.5 mm long. The same 25 leads in a straight in-line row on 2.54 mm centers would span 61 mm before you add any body margin.
Toshiba’s TB6600HG uses the shrunk variant, HZIP25-P-1.00F, where the same 25 leads span 24 mm. The suffix is doing real work: it is the pitch in millimeters, not a revision code.
Reading the prefix and suffix
| Designation | What it means | Verified example |
| ZIP-n | n-lead zig-zag in-line package | 20-pin ZIP DRAM, Fujitsu MB814400A-70PZ |
| SZIP | Shrink ZIP, reduced lead pitch | Toshiba HZIP25-P-1.00F applies the same idea |
| HZIP | ZIP with an integral heatsink tab | Toshiba HZIP25-P-1.27, TB6560AHQ |
| P-ZIP | Plastic-bodied ZIP | Standard for the DRAM-era parts |
Table 1. Decoding ZIP-family designations, with a real part for each.
Wikipedia’s article also groups staggered-lead TO-220 derivatives such as TO-220S, TO-220-11 and TO-220-15 with HZIP. Treat those as a family by geometry, not by a common standard, because no single JEDEC outline covers them.
Every pin has four neighbors, not two
This is the design consequence nobody writes down. In a dual in-line or a straight single in-line package, a pin has two neighbors along its row. In a zig-zag, the two diagonal pins in the other row are physically closer than the next pin in the same row.
Toshiba states the rule explicitly for the TB6560AHQ: the term adjacent pin includes the pin diagonally closest to a given pin, so pin 3 has four adjacent pins, namely 1, 2, 4 and 5. The datasheet then lists 19 specific adjacent-pin pairs on that part where a short can draw enough current to cause smoke emission, among them pins 9 and 11, pins 11 and 13, and pins 16 and 18.
Two things follow. Creepage and clearance analysis must be done against the diagonal, not the in-row spacing. And any short-detection or fusing scheme has to assume roughly twice the number of candidate pin pairs a DIP of the same lead count would present.
[IMAGE 2: diagram of a zig-zag lead pattern with pin 3 highlighted and arrows to pins 1, 2, 4 and 5, annotated with the diagonal spacing | alt: “ZIP package pin 3 with its four adjacent pins in the staggered lead pattern”]
Where ZIP survives: power ICs
The DRAM application is gone, but the heatsinked variant is alive because a vertical package with a bolt-down tab still beats a flat package on thermal path. Toshiba’s TB6560AHQ and TB6560AFG are the same stepper driver in two packages, which makes the trade visible.
| Parameter | HZIP25-P-1.27 (TB6560AHQ) | HQFP64-P-1010-0.50 (TB6560AFG) |
| Mounting | Through-hole, vertical | Surface mount |
| Leads | 25, all connected | 64, of which 29 are no-connect |
| Weight, typical | 9.86 g | 0.26 g |
| Peak output current per phase | 3.5 A | 2.5 A |
| On-resistance, upper + lower, typical | 0.6 Ω | 0.7 Ω |
| Power dissipation, unaided | 5 W at TA = 25 °C, no heatsink | 1.7 W at TA = 25 °C, soldered leads |
| Power dissipation, best case | 43 W at TA = 25 °C, infinite heatsink | 4.2 W at TA = 25 °C, 4-layer board |
Table 2. One stepper-driver die in two packages, per Toshiba TB6560AHQ / TB6560AFG datasheet, 2014-10-01.
The last row is the argument for the package. Ten times the dissipation ceiling, same silicon, at the cost of 9.6 g of mass and a through-hole process. Both parts share a thermal shutdown that trips at a die temperature of 170 °C typical, with about ±20 °C of spread, so the extra headroom is real margin rather than a paper number.
The fin pins are electrically live
Toshiba warns that the heat-radiating fin pins on the backside of the TB6560AHQ and TB6560AFG are electrically connected to the backside of the die. Current flowing into the fin can make the IC malfunction.
The instruction is specific: if any voltage might appear between system ground and the fin, either tie the fin pins to ground or insulate them. A bolt-down HZIP tab is not automatically a safe grounding point, and a shared heatsink bar carrying several devices needs insulating washers unless every fin is at the same potential.
DRAM-era ZIP and sourcing today
The original application was memory. Wikipedia records ZIP bodies with 16, 20, 28 or 40 leads, with the ZIP-20 body around 3 mm × 30 mm × 10 mm, later displaced by TSOP. A Hitachi patent describing the era puts a 16 Mbit DRAM die of 16.48 mm × 8.54 mm into a 450 mil ZIP body, which gives a sense of how tight the packaging was.
Sourcing splits cleanly by variant. ZIP DRAM such as the 20-pin Fujitsu MB814400A-70PZ now moves through independent distributors and marketplace listings rather than franchise channels, with no manufacturer support behind it. HZIP power parts remain available through authorized distribution; the TB6560AHQ datasheet is hosted by Mouser under an authorized-distributor notice.
For a repair or a legacy build, that difference matters more than price. A ZIP DRAM bought loose has no lot traceability and no way to verify the grade beyond the laser mark. A ZIP-family power IC bought through franchise has both.
[IMAGE 3: a 20-pin ZIP DRAM chip beside a modern HZIP25 motor driver, showing the shared staggered-lead geometry across three decades | alt: “ZIP package DRAM chip beside a modern HZIP25 motor driver IC”]
Design mistakes that cause returns
- Drilling one row of holes on 1.27 mm centers. The face-on pitch is 1.27 mm; the holes are two staggered rows on 2.54 mm centers.
- Running creepage analysis against in-row spacing when the diagonal pin is closer.
- Treating an HZIP fin as an inert mounting tab rather than a node tied to the die backside.
- Reading a Toshiba HZIP suffix as a revision. HZIP25-P-1.27 and HZIP25-P-1.00F are different lead pitches and different body lengths.
- Sizing the thermal budget from the unaided figure when the part is specified for a heatsink, or the reverse.
- Ordering ZIP DRAM from marketplace listings for anything that has to be supportable.
Frequently asked questions
What is a ZIP package in electronics?
A zig-zag in-line package: a through-hole IC package whose leads all exit one long edge in two staggered rows, letting the part stand vertically on the board. It was introduced for DRAM to raise mounting density and now appears mainly as HZIP, the heatsinked power variant used for motor drivers and regulators.
What is the difference between ZIP and SIP?
Both bring every lead out of one side of the body. A single in-line package puts them in one straight row; a ZIP staggers them into two rows. The stagger halves the edge length for a given lead count, which is why a 25-lead ZIP body runs about 36.5 mm rather than over 61 mm.
What does HZIP mean?
HZIP is a ZIP with an integral heatsink tab. The letter H denotes the heatsink, as S denotes a shrunk pitch and P denotes a plastic body. On Toshiba parts the trailing number is the lead pitch in millimeters, so HZIP25-P-1.27 is a 25-lead HZIP on 1.27 mm pitch.
What is the ZIP package pin pitch?
Viewed face-on, adjacent leads are 1.27 mm apart. On the board they land in two staggered rows with 2.54 mm between holes in the same row. Shrunk variants exist: Toshiba’s HZIP25-P-1.00F uses a 1.00 mm projected pitch, giving a 24 mm lead span for 25 leads.
Are ZIP packages still made?
The memory version is obsolete and sold only through independent channels. The heatsinked version is current: Toshiba still catalogues stepper drivers such as the TB6560AHQ in HZIP25-P-1.27, and those parts are available through authorized distribution.
What to do next
If you are laying out a new board with an HZIP power IC, draw the two staggered hole rows from the manufacturer’s outline rather than from a generic ZIP pattern, check the diagonal spacing against your creepage requirement, and confirm what the fin pins are tied to before you bolt them to a shared heatsink.
If you are repairing DRAM-era hardware, source the part and accept that support ended decades ago. If the design is new and the ceiling is under about 5 W, a surface-mount package will cost less and place faster. Reach for the ZIP package family when the thermal path, not the footprint, is the binding constraint.
Primary sources
- Toshiba TB6560AHQ / TB6560AFG datasheet (HZIP25 power, fin pins, adjacent-pin rule) — https://www.mouser.com/datasheet/2/408/TB6560AHQ_datasheet_en_20141001-771503.pdf
- Toshiba HZIP25-P-1.00F package page (dimensions and packing) — https://toshiba.semicon-storage.com/us/semiconductor/design-development/package/detail.HZIP25-P-1.00F.html
- Toshiba TB6600HG datasheet (HZIP25-P-1.00F, 7.7 g typical) — https://www.makerguides.com/wp-content/uploads/2019/10/TB6600HG-Datasheet.pdf
- Wikipedia, Zig-zag in-line package (lead counts, ZIP-20 body, HZIP grouping) — https://en.wikipedia.org/wiki/Zig-zag_in-line_package
- US Patent 5,863,817 (16 Mbit DRAM die in a 450 mil ZIP body) — https://image-ppubs.uspto.gov/dirsearch-public/print/downloadPdf/5863817
Proposed internal links
- [INTERNAL LINK: “SIP and single in-line packages” → SIP package reference page]
- [INTERNAL LINK: “TO-220 and its staggered-lead variants” → TO-220 package guide]
- [INTERNAL LINK: “creepage and clearance for through-hole packages” → PCB spacing and safety guide]
- [INTERNAL LINK: “heatsinking through-hole power ICs” → thermal design guide]
- [INTERNAL LINK: “sourcing obsolete memory safely” → component authentication and sourcing guide]
