The TSSOP-20 package is a 20-lead thin shrink small outline package registered to JEDEC MO-153, variation AC. The plastic body measures 4.4 mm × 6.5 mm, the lead span is 6.4 mm, the pitch is 0.65 mm and the seated height is 1.2 mm maximum. Below are the outline dimensions, the pin-numbering rules, six vendor land patterns side by side, and the thermal and routing numbers that decide whether TSSOP-20 survives your constraints.

Key takeaways

• Variation AC fixes the outline: 4.4 mm × 6.5 mm body, 6.4 mm lead span, 0.65 mm pitch, 1.2 mm maximum height. Only the body length separates it from TSSOP-16.
• Six suppliers publish six different land patterns. Toe-to-toe span runs from 6.60 mm (Analog Devices) to 7.72 mm (Diodes) — a 1.12 mm spread on one JEDEC outline.
• TSSOP-20 is not the thermal loser people assume. On the SN74LV245A die it beats SSOP-20, TVSOP-20 and VSSOP-20, and lands within 6% of wide-body SOIC-20.
• The thermal ranking flips with lead count. On a 16-lead die TI measures TSSOP worse than SSOP; on this 20-lead die it is better. Read the table, not the family name.
• TSSOP-20 ships in 16 mm carrier tape, not the 12 mm tape TSSOP-16 uses. That is a feeder change on the line.
• Its ψJT of 2.2 °C/W makes junction temperature measurable with a top-surface thermocouple. SSOP-20 at 39.3 °C/W does not.

[IMAGE 1: Dimensioned TSSOP-20 outline, top and side views, with A, A1, D, E, E1, e and L called out | alt: “TSSOP-20 package dimensions: 4.4 mm x 6.5 mm body, 6.4 mm lead span, 0.65 mm pitch”]

TSSOP-20 dimensions (JEDEC MO-153, variation AC)

TSSOP-20 is a 20-lead gull-wing surface-mount package with a 4.4 mm wide by 6.5 mm long plastic body, a 6.4 mm nominal lead span, 0.65 mm lead pitch and a 1.2 mm maximum seated height. Ten leads sit on each long side. Both Monolithic Power Systems and Analog Devices name the registration explicitly as MO-153, variation AC.

Table 1. TSSOP-20 outline dimensions, in millimeters

Symbol	Feature	Min	Max	Source and notes
A	Seated height	—	1.20	TI, Diodes, MPS, Renesas; Analog Devices caps its F package at 1.10
A1	Standoff	0.05	0.15	Agreed across all six drawings
A2	Body thickness	0.80	1.05	Diodes and MPS; Renesas gives 0.90 +0.15 / −0.10
b	Lead width	0.19	0.30	TI, Diodes, MPS, ADI; Renesas gives 0.25 +0.05 / −0.06
c	Lead thickness	0.09	0.20	Diodes, MPS, ADI
D	Body length	6.40	6.60	6.50 nominal — the only axis that differs from TSSOP-16
E	Lead span	6.20	6.60	6.40 BSC nominal
E1	Body width	4.30	4.50	4.40 nominal
e	Lead pitch	0.65 BSC	0.65 BSC	18 spaces, 9 per side, 5.85 mm lead field per side
L	Foot length	0.45	0.75	0.60 nominal; TI starts at 0.50
θ	Lead angle	0°	8°	Gull-wing form
—	Coplanarity	—	0.10	MPS drawing MF-PO-D-0005

TSSOP-20 shares its 4.4 mm width, 6.4 mm lead span and 1.2 mm height ceiling with every other 4.4 mm TSSOP. It is 1.5 mm longer than TSSOP-16 to fit four more leads at the same pitch.

Height is the one dimension worth checking per supplier. Analog Devices caps its 20-lead F package at 1.10 mm maximum against the 1.20 mm JEDEC ceiling, and NXP describes SOT360-1 as a 1.1 mm body. If your enclosure gap is tight, that 0.10 mm is free margin you only get by reading the specific drawing.

One housekeeping note that matters for procurement documents: JEDEC lists MO-153 at issue I, August 2024, under a title that now covers TSSOP and HTSSOP together. Citing “MO-153” without an issue letter is fine for geometry, not for a compliance statement.

TSSOP-20 pinout: what the package fixes, and where it stops

A package has no pinout. TSSOP-20 fixes lead count, geometry and numbering direction; the device decides what each lead does.

Numbering runs counter-clockwise from the pin 1 index area, viewed from the top: pins 1 to 10 down one side, then 11 to 20 back up the other. Pin 1 sits at the top left, marked by a moulded dimple, a bevelled corner, or both.

The SN74LV245A shows how far the abstraction reaches. TI publishes one pin map for its DB, DGV, DW, N, NS, PW and DGS packages together — DIR on pin 1, GND on pin 10, B8 on pin 11, VCC on pin 20. Seven different bodies, one pin map, because all seven are dual-row gull-wing parts.

That stops at the VQFN versions. The same device in RGY or RKS renumbers around four sides and adds an exposed pad, so a schematic symbol built for the TSSOP will not drop onto the QFN. Check the pin table, not the package family, before you swap.

Mirror the footprint for bottom-side placement. And note that while TSSOP-16 and TSSOP-14 share one body, TSSOP-20 is visibly longer at 6.5 mm — though still indistinguishable at a glance from a 20-lead TVSOP, which is 0.4 mm pitch.

[IMAGE 2: Top view showing counter-clockwise pin numbering 1 to 20 with the pin 1 index area highlighted | alt: “TSSOP-20 pin numbering runs counter-clockwise from the pin 1 index mark, top view”]

TSSOP-20 footprint: six vendor land patterns compared

Every supplier publishes a recommended land for the same registered outline, and no two match. Z is the toe-to-toe span across the pattern; G is the gap between the inner pad edges.

Table 2. Recommended TSSOP-20 land patterns, in millimeters

Source	Pad L × W	Pitch	Row centres	Span Z	Gap G
Diodes Incorporated	1.78 × 0.42	0.65	5.94	7.72	4.16
Monolithic Power Systems	1.60 × 0.40	0.65	5.80	7.40	4.20
Texas Instruments PW0020A	1.50 × 0.45	0.65	5.80	7.30	4.30
Renesas M20.173	1.45 × 0.35	0.65	5.65	7.10	4.20
Richtek	1.00 × 0.35	0.65	6.00	7.00	5.00
Analog Devices (LTC F)	1.05 × 0.45	0.65	5.55	6.60	4.50

Pad length varies by 78% across this set, from 1.00 mm to 1.78 mm, and outer span by 1.12 mm. Every one of these is a qualified pattern for the same package. They differ in how much toe and heel fillet the supplier wants and how much clearance it is willing to give up to get it.

Take the device manufacturer’s pattern when one exists — that is what their assembly qualification ran on. For a house footprint covering multi-sourced parts, the TI or MPS geometry sits mid-spread and tolerates parts built to any of these drawings.

Two conditions change the answer. Diodes advises adding 0.2 mm to the Z dimension for wave or selective soldering, which buys toe fillet. The 0.35 mm pads from Renesas and Richtek buy 0.10 mm of extra routing channel in every gap instead.

There is a quiet convenience in the TI set. PW0014A, PW0016A and PW0020A all specify the same 5.8 mm row spacing and the same 1.5 mm × 0.45 mm pad; only the pad count changes. If your library is built on TI geometry, the 14, 16 and 20-lead footprints are one parametric cell.

Mask and stencil follow the drawing. TI calls non-solder-mask-defined pads preferred, with 0.05 mm mask relief all around, and specifies a 1:1 stencil aperture of 1.5 mm × 0.45 mm on a 0.125 mm stencil.

[IMAGE 3: Six vendor land patterns overlaid on one grid with Z and G dimensioned | alt: “TSSOP-20 footprint comparison, toe-to-toe span from 6.60 mm to 7.72 mm across six vendors”]

Routing 20 leads out at 0.65 mm pitch

The channel between adjacent pads is pitch minus pad width. With TI’s 0.45 mm pad that is 0.20 mm, which needs roughly 0.06 mm line and 0.07 mm space to slip a trace through. That is outside standard fabrication. With a 0.35 mm pad the channel opens to 0.30 mm and a 0.10 mm trace with 0.10 mm clearance fits on a common 4 mil process.

Route under the body instead. TI’s pattern leaves 4.30 mm between the inner pad rows over a 6.30 mm pad-row length, about 27 mm² of clear area. At 0.10 mm line and 0.10 mm space that window carries roughly 21 parallel tracks — more than the 10 nets that need to escape from each side.

Total land area is about 7.30 mm × 6.30 mm, or 46 mm² of copper before courtyard. Budget an 8.5 mm × 7.5 mm placement envelope and confirm against the drawing for the part you are actually buying.

Thermal behavior: check the number, not the family

TI characterised the SN74LV245A die in eight different 20-lead bodies on the same test board, which makes this an unusually clean comparison.

Table 3. SN74LV245A, one die, eight 20-lead packages, in °C/W

Metric	PW TSSOP	DB SSOP	DW SOIC	NS SO	DGV TVSOP	RGY VQFN
RθJA junction-to-ambient	101.5	113.1	96.2	101.1	114.8	34.1
RθJB junction-to-board	52.5	67.9	64.7	66.1	56.3	12.0
ψJT junction-to-top	2.2	39.3	40.5	37.6	0.9	0.8
RθJC bottom	—	—	—	—	—	7.1

TSSOP-20 beats SSOP-20 by 11.6 °C/W and beats both TVSOP-20 and the 20-lead VSSOP, which TI measures at 118.4 °C/W. It sits within 6% of wide-body SOIC-20 while occupying a third of the outline area. The common claim that a bigger body always runs cooler does not hold on this data.

Do not generalise it either. On a 16-lead die, TI’s SN74AHC595 datasheet puts TSSOP at 135.9 °C/W against 97.8 °C/W for SSOP — the opposite ranking. Junction-to-ambient depends on die size, lead frame and paddle geometry as much as on body outline, so the ordering is not a property of the package family.

The ψJT column carries a practical bonus. At 2.2 °C/W for TSSOP-20, a thermocouple taped to the package top reads within a couple of degrees per watt of the junction. At 39.3 °C/W for SSOP-20 that measurement is close to meaningless. If you plan to validate junction temperature on the bench rather than in simulation, TSSOP-20 is the easier package to instrument.

Worked example. Holding TJ at 125 °C in an 85 °C ambient gives (125 − 85) / 101.5 = 0.39 W of budget in TSSOP-20, against 1.17 W in the RGY VQFN on the same die. Both figures assume the JEDEC test board; a smaller board with less copper will be worse.

When 0.39 W is not enough: the exposed-pad route

HTSSOP-20 is the same outline with the lead frame die pad exposed on the bottom. TI’s PowerPAD application note SLMA002H quantifies the gain: a 20-pin SSOP handles 0.75 W in standard form and 3.25 W with an exposed pad, assuming a 150 °C junction and 80 °C ambient. That is a factor of 4.3 for a change that costs a copper pour.

The note is specific about the board work. Use thermal vias of 0.33 mm diameter or smaller so the via does not wick solder away from the joint, and expect five to nine vias to be adequate for a small die. Do not use thermal-relief spokes on those vias; connect them continuously around the barrel.

TI asks for a minimum solder joint area of 50% of the thermal pad, and reports standard processes reaching above 80% without optimisation. Size the solder-mask-defined thermal land to the maximum exposed pad in the device datasheet.

Exposed pad or not, the same note gives a usable rework recipe for 20-lead TSSOP: hot gas removal at 220 °C and 0.39 scfm after a 50 s preheat, then 10 s at temperature; replacement at 160 °C for 40 s, then 220 °C for 60 s. Preheating the board to about 160 °C makes both operations easier.

[IMAGE 4: HTSSOP-20 land pattern showing the 20 lead pads plus a solder-mask-defined thermal land and via field | alt: “HTSSOP-20 exposed pad land pattern with 0.33 mm thermal vias and no thermal relief spokes”]

TSSOP-20 against the other 20-lead options

TI publishes computed outline areas for the SN74LVC245A in each body, which turns the size argument into numbers you can defend.

Table 4. Twenty-lead package options, outline area and pitch

Package	Outline (mm)	Area (mm²)	Pitch	Height	Body (mm)
TSSOP (PW)	6.5 × 6.4	41.6	0.65	1.2 max	6.50 × 4.40
SSOP (DB)	7.2 × 7.8	56.2	0.65	2.0 max	7.20 × 5.30
SOIC (DW)	12.8 × 10.3	131.8	1.27	2.65 max	12.80 × 7.50
VSSOP (DGS)	5.1 × 5.1	—	0.50	1.1 max	5.10 × 3.00
VQFN (RGY)	4.5 × 3.5	15.8	0.50	1.0 max	4.50 × 3.50
PDIP (N)	24.33 × 9.4	228.7	2.54	through-hole	24.33 × 6.35

Against wide-body SOIC-20, TSSOP-20 cuts outline area by 68% and maximum height from 2.65 mm to 1.2 mm. Against SSOP-20 the saving is 26% of area and 0.8 mm of height, with no thermal penalty on this die. The VQFN halves the area again, but you lose inspectable joints and gain a mandatory thermal land.

A decision path in the order the constraints usually arrive:

1. Mounted height under 1.5 mm? SOIC-20 and SSOP-20 are out. TSSOP-20, VSSOP-20 or VQFN-20 remain.
2. Dissipation above roughly 0.4 W at your worst-case ambient? Plain TSSOP-20 is out. Move to HTSSOP-20 or VQFN-20.
3. Two-layer board? TSSOP-20 escapes cleanly under the body; a 20-lead VQFN generally will not.
4. Need visible joints for AOI, hand rework or field repair? TSSOP-20 beats both VQFN options.
5. All four satisfied? Take TSSOP-20, and take the land pattern from the device manufacturer’s drawing.

Packing, moisture sensitivity and supplier codes

TSSOP-20 ships in 16 mm carrier tape at 8 mm pocket pitch on a 330 mm reel, 2000 pieces. TI gives the cavity as A0 6.95 mm, B0 7.0 mm to 7.1 mm, K0 1.4 mm to 1.6 mm. TSSOP-16 uses 12 mm tape, so moving from 16 to 20 leads changes the feeder as well as the footprint.

Moisture sensitivity varies by package on the same device. TI ships SN74LV245A in TSSOP at MSL 1, 260 °C with unlimited floor life, but the RGY VQFN version at MSL 2, 260 °C, one year. Read the package option addendum for the exact orderable part number rather than assuming the device rating.

Table 5. TSSOP-20 designators by supplier

Supplier	Package code	Notes
Texas Instruments	PW, PWP for the exposed pad	Drawing PW0020A, 4220206/A
Analog Devices	RU-20; F package for LTC parts	F package drawing 05-08-1650, 1.10 mm max height
Diodes Incorporated	TSSOP-20	Largest published land: Z 7.72 mm
Monolithic Power Systems	TSSOP-20	MF-PO-D-0005 r1.0, MO-153 variation AC
Renesas	M20.173	Smallest published pad width: 0.35 mm
NXP / Nexperia	SOT360-1	6.5 × 4.4 × 1.1 mm body, 0.65 mm pitch
Toshiba	TSSOP20	Land pattern to JEITA ET-7501 level 3

Seven mistakes that send TSSOP-20 boards back

• Copying a library footprint without checking Z and G against the device drawing. The spread across suppliers is over a millimeter.
• Assuming a TSSOP-20 footprint accepts a 20-lead TVSOP. The pitch is 0.4 mm, not 0.65 mm.
• Reusing a TSSOP-16 feeder setup for TSSOP-20. The tape is 16 mm wide, not 12 mm.
• Assuming SSOP-20 runs cooler because it is bigger. On the SN74LV245A it runs 11.6 °C/W hotter.
• Swapping to the VQFN version of the same part without re-checking the pin table. QFN numbering does not follow the dual-row map.
• Putting thermal-relief spokes on the vias under an HTSSOP-20 thermal land.
• Wave soldering on a reflow-sized land without adding 0.2 mm to Z.

TSSOP-20 FAQ

What are the dimensions of a TSSOP-20 package?

The body is 6.5 mm long by 4.4 mm wide, with a 6.4 mm lead span across the formed leads, 0.65 mm pitch and a 1.2 mm maximum seated height. Standoff runs 0.05 mm to 0.15 mm and foot length 0.45 mm to 0.75 mm. It is registered to JEDEC MO-153, variation AC.

What is the difference between TSSOP-16 and TSSOP-20?

Only body length and lead count. Both are 4.4 mm wide with a 6.4 mm lead span, 0.65 mm pitch and 1.2 mm maximum height. TSSOP-16 is 5.0 mm long; TSSOP-20 is 6.5 mm. On TI geometry both use the same 5.8 mm land row spacing and the same pad size, so the footprints differ only in pad count.

Is TSSOP-20 the same as SSOP-20?

No. Both use 0.65 mm pitch, but SSOP-20 is larger everywhere else. TI’s DB0020A drawing gives a 5.0 mm to 5.6 mm body width, 7.4 mm to 8.2 mm lead span and 2.0 mm maximum height, against 4.3 mm to 4.5 mm, 6.2 mm to 6.6 mm and 1.2 mm for TSSOP-20. Different land patterns, not interchangeable.

How much power can a TSSOP-20 dissipate?

About 0.39 W if you hold the junction at 125 °C in an 85 °C ambient, using the 101.5 °C/W measured on the SN74LV245A on a JEDEC board. Real boards with less copper do worse. An exposed-pad HTSSOP-20 with a proper thermal land and vias moves that figure up by roughly a factor of four.

Can you hand-solder a TSSOP-20?

Yes. At 0.65 mm pitch the leads stay visible and reachable with a fine tip. Tack opposite corners, drag-solder each row of ten, then wick the excess. Because the joints remain inspectable under a stereo microscope, TSSOP-20 is far more prototype-friendly than the 20-lead VQFN alternatives.

What is the footprint size for TSSOP-20?

Using the TI pattern, copper occupies about 7.30 mm across the pad rows by 6.30 mm along them, roughly 46 mm² before courtyard. Diodes calls for 7.72 mm across and Analog Devices 6.60 mm. Budget an 8.5 mm × 7.5 mm placement envelope and verify against the drawing for your specific device.

What to do next

Choose TSSOP-20 when mounted height must stay under 1.2 mm, dissipation stays below roughly 0.4 W at your worst-case ambient, and you want joints you can inspect and rework. It is the densest package in the 20-lead set that still lets a two-layer board escape all twenty nets.

Pull the land pattern from the device manufacturer’s drawing and check Z and G against Table 2 before release. If the thermal margin is thin, specify the exposed-pad variant now: the lead pattern is unchanged, so the cost today is a copper pour and a via field rather than a re-spin after the first chamber run.

Sources

• Texas Instruments, PW0020A package drawing 4220206/A, MPDS362A: https://www.ti.com/lit/pdf/mpds362a
• Texas Instruments, SN74LV245A datasheet SCLS382R: https://www.ti.com/lit/ds/symlink/sn74lv245a.pdf
• Texas Instruments, PowerPAD Thermally Enhanced Package, SLMA002H: https://www.ti.com/lit/pdf/slma002
• Diodes Incorporated, TSSOP-20 package outline, rev. 2019-04-02: https://www.diodes.com/assets/Package-Files/TSSOP-20.pdf
• Monolithic Power Systems, 20-TSSOP outline MF-PO-D-0005 rev. 1.0: https://media.monolithicpower.com/cms_document/Package%20Information/TSSOP-20%20POD.pdf
• Renesas, package drawing M20.173 Rev. 2: https://www.renesas.com/en/document/psc/package-drawing-tssop-20pin-m20173
• Analog Devices, 20-lead plastic TSSOP F package, LTC DWG 05-08-1650: https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-tssop/tssop_20_05-08-1650.pdf
• Richtek, TSSOP-20 footprint drawing: https://www.richtek.com/assets/podfiles/Footprint-TSSOP-20.pdf

Internal links to place

• [INTERNAL LINK: TSSOP-16 package dimensions -> TSSOP-16 dimensions, pinout and footprint]
• [INTERNAL LINK: SSOP-20 land pattern -> SSOP package dimensions and footprint guide]
• [INTERNAL LINK: thermal vias under an exposed pad -> exposed-pad and PowerPAD thermal design guide]
• [INTERNAL LINK: moisture sensitivity level and floor life -> J-STD-020 MSL handling guide]
• [INTERNAL LINK: reading a JEDEC package outline drawing -> JEDEC package outline explainer]