The TSOP-48 package is a Type I outline: 48 gull-wing leads on 0.50 mm pitch, 24 per short edge, a 12 mm body width, an 18.4 mm body length and a 20.0 mm lead span. ONFI pins the geometry down further, to JEDEC MO-142 variation DD. The dimensions are the easy part. Three mutually incompatible pin maps share this one footprint, and telling them apart is what this page is for.
Key takeaways
- Body 12 × 18.4 mm, lead span 20.0 mm, pitch 0.50 mm, maximum seated height 1.20 mm.
- The ONFI specification names the exact registration: MO-142 variation DD.
- Three pin maps use this outline: NOR standard, NOR reverse, and the ONFI NAND assignment. None is compatible with the others.
- AMD and Spansion distinguished standard from reverse by one character in the ordering code.
- ONFI’s 16-bit TSOP-48 cannot support the source-synchronous data interfaces. Only the 8-bit version can.
- WSOP-48 shares the ONFI pin assignment but is registered separately, under MO-259.
[IMAGE 1: TSOP-48 outline with 24 leads per short edge, 20 mm lead span and 0.5 mm pitch dimensioned | alt: “TSOP-48 package dimensions showing 0.5 mm pitch, 12 mm body width and 20 mm lead span”]
What a TSOP-48 package is
A TSOP-48 package is a 48-lead thin small outline package, Type I, with 24 gull-wing leads on each of the two shorter edges at 0.50 mm pitch and a maximum seated height of 1.20 mm. It is the standard leaded package for parallel NOR and parallel NAND flash. The ONFI specification states that the physical dimensions come from JEDEC document MO-142 variation DD.
That variation letter is worth having. MO-142 covers Type I at 24, 32, 40, 48 and 56 leads, and quoting the registration alone does not identify the size. ONFI’s reference resolves it in one string, and the same sentence has appeared unchanged from revision 2.0 in February 2008 through revision 5.2 in February 2024.
TSOP-48 dimensions
| Parameter | Value | Source |
| Body width | 12.0 ± 0.1 mm | Renesas drawing PTSA0048KF |
| Body length | 18.4 ± 0.1 mm | Renesas drawing PTSA0048KF |
| Lead span | 20.0 ± 0.2 mm | Renesas drawing PTSA0048KF |
| Pitch | 0.50 mm | MO-142 variation DD, per ONFI |
| Leads per edge | 24 | — |
| Max seated height | 1.20 mm | Renesas drawing PTSA0048KF |
| Body thickness | 1.00 ± 0.05 mm | Renesas drawing PTSA0048KF |
Distributor records corroborate the outline from two directions. Spansion’s AM29F160DB in 48-pin TSOP is catalogued at 12 × 18.4 × 1 mm, and Infineon’s S34ML01G100TFI000 SLC NAND at 18.5 × 12.1 × 1.05 mm, which are the same package quoted at nominal and at maximum.
Two numbers to keep straight: 18.4 mm is the body length and 20.0 mm is the lead span. Descriptions that write the package as “12 × 20 mm” are giving width and span, not width and length.
Three incompatible pinouts share this footprint
Here is the part that costs boards. The same 48-lead outline carries at least three different pin assignments.
| Pin map | Defined by | Typical devices | Ordering clue |
| NOR standard | Vendor datasheet, drawing TS 048 | Am29F400B, Am29F160D, S29GL064N | Package code E on AMD and Spansion parts |
| NOR reverse | Vendor datasheet, drawing TSR048 | Same dice, mirrored pin order | Package code F on the same parts |
| NAND, ONFI | ONFI specification, Figures 2 and 3 | MT29F, S34ML01G, MX30LF | ONFI revision quoted in the part’s parameters |
The AMD and Spansion Am29F400B ordering scheme spells the first two out: E is the 48-pin TSOP standard pinout, drawing TS 048, and F is the 48-pin TSOP reverse pinout, drawing TSR048. One character in a 15-character part number decides whether the address bus arrives at the correct end of your footprint.
The programming ecosystem treats these as three separate devices, which is the practical tell. Elnec lists the Am29F400BB under a distinct R-TSOP48 entry and sells a dedicated DIL48/TSOP48 ZIF adapter for NAND with ONFI pinout, rated at 10,000 socket actuations. If a tool vendor needs three sockets for one package, a board designer needs three checks.
A NOR part and a NAND part will both physically solder onto a compliant TSOP-48 land pattern. Neither will work in the other’s circuit.
What the ONFI pinout constrains
Two clauses in the specification matter at design time.
The 16-bit version gives up the fast interfaces. ONFI defines separate 48-pin TSOP pin assignments for 8-bit and 16-bit data access, and states that the 16-bit package does not support the source-synchronous data interface. In current revisions the same restriction is written against NV-DDR, NV-DDR2, NV-DDR3 and NV-LPDDR4. If you need a x16 NAND bus in this package, you are choosing the asynchronous interface at the same time.
Pin 35 changes meaning by device class. The specification notes that on a part capable of the double-data-rate interfaces, pin 35 is unused when the device runs in the asynchronous interface, and that VSP2 is present on SDR-only parts. Treat pin 35 as vendor-and-mode dependent and read it off the specific datasheet rather than a generic ONFI figure.
[IMAGE 2: TSOP-48 top view comparing the NOR standard, NOR reverse and ONFI NAND pin maps | alt: “TSOP-48 package pinout comparison showing NOR standard, NOR reverse and ONFI NAND assignments”]
WSOP-48, the thinner sibling
ONFI covers the 48-pin WSOP in the same pin-assignment figures as the TSOP, so the two share a pin map. The dimensions are registered separately, under JEDEC MO-259, which the JEP95 index lists as a very very thin small outline Type I package at 48 leads.
Shared pin assignment does not mean a shared land pattern. Take both drawings before you assume one footprint serves both. Where height is the binding constraint, WSOP-48 is the option to look at first, and it is the only one that keeps the ONFI pin map without moving to an area array.
Footprint: what carries over
The land pattern for this outline is the same one that serves every 0.50 mm pitch Type I part, because pitch, lead span, lead width and foot length are common across the family. At IPC-7351B nominal density the result is a 0.35 mm × 1.65 mm pad on a 19.25 mm row centreline, with 0.15 mm of clearance between adjacent pads. The derivation is on the TSOP Type I page and does not change for 48 leads.
Two consequences specific to this size. Twenty-four pads per row give a 11.85 mm pad array, which fits inside the 12 mm body width with the family’s usual 0.25 mm margin at each end. And at 0.15 mm clearance no track passes between pads at standard rules, so all 48 nets escape outward or drop to an inner layer through a via each.
Sourcing and second sources
NAND in this package is current. Infineon’s S34ML01G100TFI000, a 1 Gbit SLC NAND with an ONFI 1.0 interface, is a live catalog part. Micron’s MT29F family is filed by DigiKey under the package field 48-TSOP I, and supply is uneven within it: the MT29F2G08ABAEAWP:E shows out of stock with backorders unavailable and a per-30-day purchase limit.
NOR in this package is thinning. RS no longer stocks the Spansion AM29F160DB-75EI. The Am29F400B datasheet, publication 21505 revision E amendment 8 dated 11 November 2009, is distributed under an end-of-life filename.
Macronix publishes direct replacements for several 48-TSOP NOR parts in its cross-reference guide:
| Original part | Package options | Recommended replacement |
| AM29SL800D | 48-TSOP, 48-LFBGA, 48-TFBGA | MX29SL800C |
| S29AS008J | 48-TSOP, 48-LFBGA, KGD | MX29SL800C |
| S29AS016J | 48-TSOP, 48-LFBGA, 48-TFBGA, KGD | Contact Macronix |
One search hazard applies to this keyword more than any other in the family. Vishay’s TSOP48xx series are infrared receiver modules, and TSOP4838 is among the most widely used. A distributor search for “TSOP48” returns them first. Filter by category, or search the package field.
Five mistakes on TSOP-48 designs
- Assuming one pinout. Three pin maps share this outline. Confirm which one before routing.
- Missing the E-versus-F ordering code. Standard and reverse NOR differ by one character and are not interchangeable.
- Specifying x16 ONFI NAND and a fast interface. The 16-bit TSOP-48 does not support the source-synchronous or NV-DDR interfaces.
- Treating WSOP-48 as a drop-in. Same pin map, different registration. Compare the drawings.
- Ordering by “TSOP48” at a distributor. You will get infrared receivers.
TSOP-48 FAQ
What are TSOP-48 package dimensions?
Body 12.0 ± 0.1 mm wide by 18.4 ± 0.1 mm long, lead span 20.0 ± 0.2 mm, lead pitch 0.50 mm, maximum seated height 1.20 mm, body thickness 1.00 ± 0.05 mm, with 24 leads on each short edge. ONFI ties the geometry to JEDEC MO-142 variation DD.
Is TSOP-48 Type I or Type II?
Type I. The leads emerge from the two shorter 12 mm edges, which is why the lead span runs along the 20 mm axis. Distributors usually write it as “48-TSOP I”. A 48-lead Type II is not a standard registration, so if a listing claims one, ask for the drawing.
What is the ONFI TSOP-48 pinout?
The pin assignment ONFI defines for 48-pin TSOP and WSOP NAND, in separate figures for 8-bit and 16-bit data access. It has been stable in wording from revision 2.0 in 2008 to revision 5.2 in 2024. The 16-bit variant does not support the source-synchronous or NV-DDR data interfaces.
What is a reverse TSOP?
A package with the same outline and a mirrored pin order, offered so a part can be mounted on the opposite side of a board or match an existing layout. AMD and Spansion sold both from the same die: package code E was the standard pinout, drawing TS 048, and code F the reverse pinout, drawing TSR048.
Is TSOP-48 the same as WSOP-48?
They share the ONFI pin assignment but not the registration. TSOP-48 is JEDEC MO-142 variation DD; WSOP-48 is MO-259, a very very thin Type I outline at 48 leads. Pin-for-pin compatible does not mean footprint-compatible, so compare both drawings before reusing a land pattern.
Choosing TSOP-48
Specify TSOP-48 when you need parallel NAND or NOR in a leaded, inspectable package and can give the part an escape via per net. For SLC NAND in industrial and automotive designs it remains a well-supported choice, and the ONFI pin assignment gives you genuine multi-vendor freedom that no earlier TSOP size offers.
Move to WSOP-48 if height is the constraint and you want to keep the pin map. Move to an ONFI BGA if you need the double-data-rate interfaces or a x16 bus at speed.
Before you place the footprint, run three checks in order: confirm the part is Type I and take the 20.0 mm lead span rather than the 18.4 mm body, identify which of the three pin maps the device uses, and check the ordering code for a standard-versus-reverse suffix. The first is a footprint error, the second and third are silent ones that pass visual inspection and fail at power-up.
[IMAGE 3: TSOP-48 land pattern with 48 fanout vias and the two end escape channels | alt: “TSOP-48 package footprint showing fanout vias at both short-edge lead rows”]
Internal links to add
- [INTERNAL LINK: TSOP package → the full TSOP family, registrations and land patterns]
- [INTERNAL LINK: TSOP Type I → short-side lead layout and the land pattern derivation]
- [INTERNAL LINK: TSOP-32 package → the 32-lead outline and its five registrations]
- [INTERNAL LINK: TSOP Type II → long-side lead layout and the 400-mil family]
- [INTERNAL LINK: NAND flash package selection → TSOP-48 against ONFI BGA]
