The TO-252 package — everyone calls it DPAK — is a 6.10 mm × 6.58 mm molded body with three gullwing leads on 2.286 mm centers and an exposed tab that carries the third terminal and nearly all the heat. Published land patterns occupy about 7 mm × 11 mm. Below are the verified dimensions, two vendor footprints side by side, and the copper-area decision that moves this package’s thermal rating by more than 5:1.

Key takeaways

• Body 6.10 mm × 6.58 mm × 2.29 mm typical, pitch 2.286 mm BSC, overall lead span 9.91 mm typical (Diodes Inc., TO252 (DPAK) Package Information, Rev. 2022-05-10).
• Nexperia publishes the DPAK reflow footprint as 7 mm × 11 mm — 77 mm² of board — with a recommended stencil thickness of 0.125 mm.
• The tab is a live terminal (drain, collector or cathode depending on style), not a mounting pad.
• θJA is 132.2 °C/W on a JEDEC 1s board and 23.2 °C/W on a 2s2p board — same package, same standard (ROHM 64AN140E, April 2022).
• “TO-252-5” is not one thing: Diodes uses 1.27 mm pitch, Infineon uses 1.14 mm.

[IMAGE 1: dimensioned top and side view of the 3-lead package with A, D, E, e, H and L callouts | alt: “TO-252 (DPAK) package dimensions showing 6.10 mm body, 2.286 mm lead pitch and exposed tab”]

What the TO-252 package is

TO-252 is a JEDEC transistor outline for a plastic, single-ended surface-mount power package with three leads and an exposed metal tab. It is known industry-wide as DPAK. Nexperia calls it SOT428, onsemi CASE 369C, Infineon PG-TO252-3-11. The tab both conducts current and removes heat.

Motorola developed it as the surface-mount counterpart to the through-hole TO-251/IPAK and as the small sibling of TO-263. Today it carries medium-power MOSFETs, Schottky and fast-recovery diodes, linear regulators, bipolar transistors and triacs.

Designation	Who uses it
TO-252, TO-252-3	JEDEC outline family name
DPAK, DPAK-3	Universal industry name
SOT428, SOT428-2	Nexperia (formerly NXP)
CASE 369A, 369C	onsemi
PG-TO252-3-11	Infineon
SC-63	JEITA / EIAJ naming

Table 1 — What the same package is called.

TO-252 package dimensions

Symbol	Parameter	Min	Typ	Max
A	Overall height	2.19	2.29	2.39
A1	Standoff	0.00	0.08	0.13
A2	Body thickness	0.97	1.07	1.17
b	Lead width	0.64	0.783	0.88
b3	Tab width	5.21	5.33	5.50
c	Lead thickness	0.45	0.531	0.58
D	Body length	6.00	6.10	6.20
E	Body width	6.45	6.58	6.70
e	Lead pitch	—	2.286 BSC	—
H	Overall span, lead tip to tab	9.40	9.91	10.41
L	Foot length	1.40	1.59	1.78

Table 2 — TO-252 (DPAK-3) outline, all values in mm. Source: Diodes Incorporated, TO252 (DPAK) Package Information, Rev. 2022-05-10.

Cross-check the envelope before committing. Nexperia’s SOT428-2 sheet gives D 5.98–6.22, E 6.40–6.73 and seated height 2.20–2.40 mm — the same package. onsemi’s current drawing is titled DPAK−3 6.10×6.54×2.28, 2.29P (CASE 369C, Issue K, 14 May 2026).

The odd metric typicals have a reason. onsemi’s CASE 369A-13 states the controlling dimension is inch, per ANSI Y14.5M-1982: 2.286 mm is 0.090 in, and the 4.58 mm BSC across the outer leads is 0.180 in. Anything you round to “2.3 mm” accumulates error against a footprint drawn from the inch original.

Note that ROHM quotes the same package as 6.5 mm × 9.5 mm × 2.5 mm. That figure includes the leads. Always confirm whether a “size” is body-only or lead-inclusive.

Pinout and the ten registered styles

onsemi’s CASE 369C registers ten pin styles against one outline. Pin 4 is always the tab.

• Style 1: base, collector, emitter, collector
• Style 2: gate, drain, source, drain — the MOSFET case
• Style 3: anode, cathode, anode, cathode
• Style 4: cathode, anode, gate, anode
• Style 6: MT1, MT2, gate, MT2 — a triac
• Style 9: anode, cathode, resistor adjust, cathode — a shunt regulator

The consequence is blunt: do not infer a pinout from the package. Two DPAKs from the same tape format can have different center pins and different tab nets. Read the device datasheet, not the outline.

The TO-252 land pattern

Two vendors publish footprints for the identical package, and they agree closely enough to trust.

Feature	Diodes suggested pad layout	Nexperia reflow footprint (SOT428-2)
Tab land	5.632 mm wide × 5.700 mm long	Solder land inside 6.15 mm × 5.75 mm envelope
Lead pads	1.060 mm × 2.600 mm, three off	1.5 mm × 2.4 mm class
Outer pad centers	4.572 mm	4.57 mm
Overall pattern	10.700 mm long	7 mm × 11 mm occupied area, 77 mm²
Stencil thickness	Not specified	0.125 mm recommended
Wave soldering	Add 0.2 mm to the Z dimension	Separate footprint published

Table 3 — Published TO-252 land patterns. Sources: Diodes Rev. 2022-05-10; Nexperia SOT428-2, 16 January 2025.

Diodes’ 10.700 mm overall length and Nexperia’s 11 mm occupied dimension are the same footprint described two ways. Both vendors state the pattern is reference guidance and point to IPC-7351A; both expect you to adjust for your assembly capability.

Copy all four layers from the vendor drawing, not just the copper. Nexperia’s footprint separates solder land, solder resist, solder paste and occupied area — the paste and mask geometries are not derivable from the copper alone, and guessing them is how tab voiding and tombstoned leads start.

The tab land at 5.632 mm × 5.700 mm is 32.1 mm² of copper. Add three lead pads and a bare footprint gives roughly 40 mm² total. Hold that number for the next section.

[IMAGE 2: recommended land pattern with pad dimensions annotated | alt: “TO-252 DPAK land pattern showing 5.632 mm by 5.700 mm tab land and three lead pads on 4.572 mm centers”]

Thermal: copper area decides the part

ROHM measured TO-252 under JESD51-2A still air on the two standard boards, JESD51-3 and JESD51-7.

Board	Copper	θJA (°C/W)	ΨJT (°C/W)	Max P at 150 °C junction, 85 °C ambient
1s (single layer)	Footprint only, 49 mm², 70 µm	132.2	13	0.49 W
2s2p (four layer)	5,505 mm² planes, 70/35 µm	23.2	2	2.80 W

Table 4 — TO-252 thermal resistance by JEDEC board. Source: ROHM 64AN140E Rev.001, April 2022. Dissipation calculated as ΔT / θJA.

The same silicon in the same plastic handles 5.7 times the power. Nothing about the package changed — only the board it sits on. When a datasheet quotes a single θJA, find the board footnote before you use the number, and assume the worst case if there isn’t one.

ROHM’s 49 mm² footprint-only case is within rounding distance of the roughly 40 mm² a bare vendor land pattern gives you. If you place a DPAK on a two-layer board with no copper pour beyond the footprint, plan around 130 °C/W, not the headline figure.

The same note sweeps top-layer copper from 49 mm² to 1,200 mm² on one layer, and inner and bottom copper from 100 mm² to 5,505 mm² on 2-, 4-, 6- and 8-layer stacks. Returns flatten as area grows. A separate study runs from no via to an 8 × 7 array of Ø0.30 mm vias under the tab, which is the cheapest improvement available once the top-layer pour stops helping.

Use ΨJT for verification on real hardware. Touch a fine thermocouple to the center of the plastic top, multiply by dissipated power, add to the reading. At 13 °C/W on a single-layer board, a part burning 1 W runs 13 °C hotter inside than the case reads.

[IMAGE 3: junction-to-ambient thermal resistance plotted against copper area for one, two and four layer boards | alt: “TO-252 thermal resistance versus PCB copper area on 1s and 2s2p JEDEC boards”]

TO-252 vs D2PAK vs LFPAK56

Nexperia publishes a footprint area for every package it makes, which makes this comparison apples to apples.

Package	Nexperia code	Footprint	Footprint area	Body (mm)	Pitch
DPAK / TO-252	SOT428-2	7 × 11 mm	77 mm²	6.1 × 6.6 × 2.3	2.286 mm
D2PAK / TO-263	SOT404	16.35 × 10.85 mm	177.4 mm²	11 × 10 × 4.3	2.54 mm
LFPAK56 / Power-SO8	SOT669	5 × 6 mm	30 mm²	3.95 × 4.9 × 1.1	1.27 mm

Table 5 — Board area for three power packages. Source: Nexperia package information sheets SOT428-2, SOT404 and SOT669.

DPAK costs 57% less board area than D2PAK. LFPAK56 costs 61% less than DPAK and stands 1.1 mm tall instead of 2.3 mm; it also carries a JEDEC outline code, MO-235.

The decision path:

• Above roughly 3 W continuous, with board area available — use TO-263.
• 0.5 W to 3 W, or you need hand rework, wave-solder compatibility, or an existing footprint — use TO-252.
• Area- or height-constrained, reflow-only assembly, and you can accept a clip package — use LFPAK56.

[IMAGE 4: three footprints drawn to the same scale | alt: “TO-252 DPAK, D2PAK and LFPAK56 PCB footprint areas compared at 77, 177 and 30 square millimeters”]

Variants, and the 5-lead trap

TO-252-3 is the default; unqualified “DPAK” means the 3-lead part. Two 5-lead variants exist, and their pitch is not standardized between vendors:

• Diodes TO252-5: e = 1.27 mm typical, body identical to the 3-lead at 6.10 × 6.58 × 2.29 mm (Rev. 2017-04-04).
• Infineon P/PG-TO252-5-311: 1.14 mm pitch, 4.56 mm across the outer leads.

Both ship as “TO-252-5”. A generic library footprint fits one and not the other, and the failure shows up on assembled boards, not in DRC.

Several widely copied references also claim that all TO-252 packages use a 1.27 mm pitch. That is the 5-lead figure applied to the wrong part. The 3-lead DPAK is 2.286 mm BSC, confirmed independently by Diodes, Nexperia and onsemi.

The through-hole cousin is IPAK / TO-251, drawn by onsemi as CASE 369D and labelled “DPAK insertion mount”: same body, straight leads, no gullwing.

Assembly, compliance and sourcing

• Reflow: Diodes specifies +260 °C for 30 s per JEDEC J-STD-020. Infineon rates its DPAK MOSFETs MSL 1 up to 260 °C peak.
• Materials: molded plastic rated UL 94V-0; matte tin plated leads, solderable per MIL-STD-202 Method 208.
• Automotive: DPAK discretes are routinely AEC-Q101 qualified — Infineon’s IPD5N25S3430ATMA1 is a current example.
• Packing: 16 mm embossed carrier tape, 2,500 per 13-inch reel. Tubes hold 80 (Diodes) or 300 with 4 tubes per box (Infineon). Each device weighs about 0.33 g.
• Counterfeit screening: the case outline defines the marking fields — device code, assembly location, wafer lot, year, work week, and the Pb-free “G” or microdot. Diodes’ packing spec forbids mixed date codes and two or more consecutive missing parts in a reel; both are cheap incoming-inspection checks.

Design mistakes that cause returns

• Pulling a footprint from a generic library without checking pitch — the 1.14 / 1.27 / 2.286 mm trap.
• Sizing tab copper for the footprint only, then quoting a datasheet θJA that was measured on a 2s2p board.
• Treating the tab as a mounting pad. It sits at drain, collector or cathode potential, and creepage to adjacent copper is a real constraint on high-voltage parts.
• Growing the tab pour without limit on a hard-switching node. That copper is a live dV/dt plate; past the point of thermal return it only radiates.
• Copying copper geometry but not solder resist and paste from the vendor footprint.
• Omitting the 0.2 mm Z extension on boards that will be wave-soldered.

FAQ

Is TO-252 the same as DPAK?

Yes. TO-252 is the JEDEC transistor outline and DPAK is the common name. Vendors add their own codes: SOT428 or SOT428-2 at Nexperia, CASE 369C at onsemi, PG-TO252-3-11 at Infineon, SC-63 in JEITA naming. All describe the same three-lead surface-mount body with an exposed tab, varying only within published tolerance.

What are the TO-252 package dimensions?

Typical values are 6.10 mm body length, 6.58 mm body width and 2.29 mm seated height, with 2.286 mm BSC lead pitch and a 9.91 mm overall span from lead tip to tab edge, per Diodes Rev. 2022-05-10. Nexperia gives the same envelope with maxima of 6.22 mm, 6.73 mm and 2.40 mm.

What is the TO-252 pinout?

It depends on the device, not the package. onsemi’s CASE 369C registers ten pin styles against a single outline, and pin 4 is always the tab. For MOSFETs, style 2 gives gate, drain, source with the tab tied to drain. Diodes, triacs and shunt regulators use different assignments entirely.

How much power can a TO-252 dissipate?

On a JEDEC 1s board, θJA is 132.2 °C/W, so a 150 °C junction in 85 °C air allows 0.49 W. On a 2s2p board, θJA falls to 23.2 °C/W and the same part handles 2.80 W. The package does not set the limit — the copper attached to the tab does.

What is the difference between TO-252 and TO-263?

TO-263, or D2PAK, is the larger version. Nexperia publishes footprints of 77 mm² for DPAK and 177.4 mm² for D2PAK, with bodies of 6.1 × 6.6 × 2.3 mm and 11 × 10 × 4.3 mm respectively. D2PAK accepts a bigger die and dissipates more; DPAK saves 57% of the board area.

What to do next

Pull the package drawing for the exact orderable part number you intend to buy, not a generic “TO-252” library part, and verify pitch and pin style against it. Then decide the tab copper before you route: if your budget is under about 0.5 W on a two-layer board, the bare footprint is enough. Above that, add a pour and via array on the tab net, and re-check θJA against the board you actually built — not the one on the datasheet.

Internal links

• [INTERNAL LINK: TO-263 (D2PAK) package → TO-263 dimensions and land pattern]
• [INTERNAL LINK: TO-220 package → TO-220 dimensions, pinout and mounting]
• [INTERNAL LINK: TO-243 (SOT-89) package → smaller surface-mount power outline]
• [INTERNAL LINK: TO-247 package → higher-power through-hole alternative]
• [INTERNAL LINK: moisture sensitivity levels → J-STD-020 reflow and MSL handling]