The TO-247 package is a through-hole power outline roughly 20 mm × 15.5 mm with three or four leads on 5.46 mm pitch and a bolt-down tab whose mounting hole sits in an insulated recess. The mechanical part is well documented — though two Vishay drawings disagree about their own JEDEC exception. The part worth your attention is the fourth pin, and Infineon has published measured numbers for what it buys.
Key takeaways
- Lead pitch is 5.46 mm BSC and the mounting hole is 3.56–3.66 mm per Vishay doc 95223.
- The hole sits in a recess (ØP1) up to 6.98 mm across — that recess is what makes the hole isolated.
- Vishay publishes two TO-247AC drawings with identical c and Q values, each naming a different one as its JEDEC exception.
- On a 45 mΩ CoolMOS C7 at 30 A, Infineon simulated turn-on energy of 70 µJ with a Kelvin connection against roughly 2× and 4× that at 2.5 nH and 5 nH of source inductance.
- In Infineon’s measurements the 4-pin result is identical whether the package stands 0 mm or 5 mm off the board. The 3-pin result is not.
- The fourth pin costs you a floating driver output that sees ±20 V or more against ground.
What the TO-247 package is
TO-247 is a JEDEC flange-mounted header outline for through-hole power semiconductors: a plastic body about 19.7–20.7 mm tall and 15.3–15.9 mm wide, leads on 5.46 mm BSC pitch, and a metal tab with a mounting hole recessed into the moulding so the screw does not contact live metal. Three-lead and four-lead versions share the body.
Naming splits by vendor and lead count. Vishay documents TO-247AC and TO-247AD together with TO-274AA in one marking document. Catalogs write TO-247-3 and TO-247-4. Toshiba calls its four-pin version TO-247-4L. Infineon markets a TO-247PLUS 4pin variant alongside the standard outline.
Toshiba’s stated rationale for TO-247-4L is the same one: separating the power-line current from the gate-drive current so the internal source-wire inductance stops affecting the gate-source voltage.
[IMAGE 1: Front, side and rear views of a 3-pin TO-247 with lead pitch, body envelope, mounting hole and the recess around it dimensioned | alt: “TO-247 package dimensions showing 5.46 mm lead pitch and the recessed isolated mounting hole”]
TO-247 package dimensions, and two drawings that disagree
| Symbol and feature | Vishay 95223, TO-247AC, rev 11 Dec 2019 | Vishay 96138, TO-247AC 3L, rev 20 Jun 2017 |
| A — body thickness | 4.65–5.31 mm | 4.65–5.31 mm |
| A2 | 1.50–2.49 mm | 1.17–1.37 mm |
| D — body height | 19.71–20.70 mm | 19.71–20.70 mm |
| E — body width | 15.29–15.87 mm | 15.29–15.87 mm |
| e — lead pitch | 5.46 mm BSC | 5.46 mm BSC |
| c — lead thickness | 0.38–0.89 mm | 0.38–0.89 mm |
| ØP — mounting hole | 3.56–3.66 mm | 3.56–3.66 mm |
| ØP1 — recess around the hole | 6.98 mm max | 7.39 mm max |
| Q | 5.31–5.69 mm | 5.31–5.69 mm |
| L — lead length | 14.20–16.10 mm | 14.20–16.10 mm |
| Declared JEDEC exception | “with exception of dimension c” | “with exception of dimension Q” |
Read the last row against the two above it. Both drawings list c as 0.38–0.89 mm and Q as 5.31–5.69 mm, yet each names a different one of those two as its exception to the JEDEC TO-247 outline. Whatever the explanation — a revision to JEDEC’s drawing between 2017 and 2019, or an error in one note — the conformance statement on a TO-247 drawing is not something to design against. Use the tabulated numbers.
The recess is the real difference. ØP1 runs to 6.98 mm on one drawing and 7.39 mm on the other, a 0.41 mm spread on the feature that determines whether your screw head and washer sit clear of the tab metal.
Cross-vendor, the core numbers agree to rounding. onsemi’s FPCN #16827 gives the TO-247 mounting hole as 3.55–3.65 mm and lead pitch as 5.45 mm BSC against Vishay’s 3.56–3.66 mm and 5.46 mm BSC. Both derive from the same inch values; neither is a real difference.
Pinout and ratings: what the outline bounds and what it does not
Three-lead TO-247 runs gate, drain, source on a MOSFET or gate, collector, emitter on an IGBT, with the tab common to the middle terminal. Four-lead versions add a source-sense or Kelvin pin that connects to the same source metal but carries no load current.
The outline bounds two electrical things and no others. The 5.46 mm lead pitch sets pin-to-pin creepage, which is why TO-247 rather than TO-220 carries 1200 V SiC parts. The recessed mounting hole isolates the screw from the tab, which is the reason the package replaced TO-218.
It bounds nothing about power. Wolfspeed’s C3M0065100K, a 1000 V 65 mΩ SiC MOSFET in TO-247-4, is listed at 113.5 W maximum dissipation. onsemi’s MJW21196G bipolar in TO-247 is rated 200 W. Same outline, nearly double the rating. Dissipation follows the die and the heatsink, not the plastic.
The 4-pin Kelvin source: what it buys, with numbers
| Source | What was tested | Published result |
| Infineon AN 2013-05, simulation | 45 mΩ CoolMOS C7, turn-on at 30 A | Eon of 70 µJ with Kelvin connection — a factor of 2 and 4 lower than with 2.5 nH and 5 nH source inductance |
| Infineon AN 2013-05, measurement | 1200 W PFC, same 45 mΩ die in both packages, 12 A SiC diode | 4-pin result identical at 0 mm and 5 mm pin length; 3-pin degrades with length |
| Infineon EVAL_2.5KW_CCM_4PIN note | CCM PFC at 1.2 kW | Up to 8% switching-loss reduction, 3.5 W saved, 0.3% extra full-load efficiency |
| Infineon TO-247 4-pin MOSFET page | Same die, 4-pin against 3-pin | 0.6% full-load efficiency gain; permits 60 mΩ to replace 45 mΩ |
| Infineon TO-247 4-pin IGBT page | IGBT discretes | More than 20% total switching-loss reduction |
Those figures span 0.3% to over 20% because they measure different things — device family, topology, and whether the number is loss or system efficiency. Take the one that matches your case, not the largest.
The mechanism is a single inequality. AN 2013-05 gives the current-slope ceiling as di/dt < (Ug − Vth) / LS, and notes it does not depend on gate resistance. Source inductance, not your gate drive, sets the limit.
Two details matter more than the headline percentages. Infineon measured effective source inductance of about 2 nH at zero pin length and 4 nH at 5 mm — so on a 3-pin part, how far the package stands off the board changes your switching loss. And even at zero pin length the 3-pin part is worse, because of the bond wire inside the package that only a separate source-sense wire can exclude.
The threshold is current. For the 45 mΩ C7, Infineon puts the point where source inductance starts to matter at around 15 A.
Infineon also sells an evaluation board that accepts physically identical devices in either 3-pin or 4-pin configuration. That is the cleanest way to get a number for your own topology rather than borrowing one from a PFC.
[IMAGE 2: Gate drive loop schematic for 3-pin and 4-pin TO-247, showing the source inductance inside and outside the loop | alt: “TO-247 package 3-pin and 4-pin gate drive loops showing source inductance excluded by the Kelvin connection”]
What the fourth pin costs: a floating driver
The product pages stop at the benefit. AN 2013-05 does not.
Referencing the driver output to source-sense means the whole output stage floats against power ground by the voltage across the source inductance. Infineon measured voltage peaks in the range of ±20 V or higher, and warns that a conventional junction-isolated monolithic driver can be latch-up sensitive at those levels.
Their answer was a two-chip driver using coreless-transformer isolation between the ground-referenced input and the floating output. A standard driver with an RC input filter is offered as the alternative.
The parts themselves are not the expensive half. Wolfspeed’s C3M0065100K, a 1000 V 65 mΩ SiC MOSFET in TO-247-4, lists from about $13.69 through Richardson RFPD. An isolated gate driver, its isolated bias rail and the board area they need will usually cost more than the step from three pins to four.
Budget for this before you commit to a 4-pin part. The package is cheap; the driver decision is not.
Worked example: sizing the driver bias network
AN 2013-05 works this through for the IPZ65R019C7, total gate charge 215 nC, at 100 kHz with a 12 V drive:
Accept 400 mV ripple on the bias rail per switching cycle
Cbias = 2 × Qg / dUC = 2 × 215 nC / 400 mV = 1.07 µF → rule of thumb ×10 = 10 µF
PGate = 2 × 0.5 × Qg × UG × f = 2 × 0.5 × 215 nC × 12 V × 100 kHz = 0.258 W
Ibias = PGate / UG = 258 mW / 11.8 V = 22 mA → round up to 40 mA
Rbias = dUC / Ibias = 400 mV / 40 mA = 10 Ω
Infineon cross-checks that 10 Ω against a 20 V spike on the source inductance, which gives a displacement current up to 2 A for a fraction of a nanosecond — acceptable in their assessment.
[IMAGE 3: Floating gate driver supply with Rbias and Cbias referenced to source-sense on a 4-pin TO-247 | alt: “TO-247 package 4-pin floating driver bias network with decoupling resistor and capacitor”]
Five mistakes that reach the bench
- Designing to a drawing’s conformance note. Two Vishay TO-247AC drawings name different exceptions while listing identical values. Use the table, not the note.
- Sizing screw hardware to ØP alone. The recess ØP1 varies by 0.41 mm between drawings and is what actually clears the washer.
- Leaving long leads on a 3-pin part. Infineon measured roughly 2 nH at zero standoff and 4 nH at 5 mm, and the loss scales with it.
- Fitting a 4-pin part to a ground-referenced driver. The output stage floats and sees ±20 V or more.
- Buying the 4-pin version below its threshold current. Under about 15 A on a 45 mΩ C7, source inductance is not what is costing you.
Frequently asked questions
What is the difference between TO-247 and TO-247AC?
TO-247 is the JEDEC family; TO-247AC is the three-lead variation most vendors build to. Vishay documents TO-247AC alongside TO-247AD and TO-274AA in a single marking document, and catalogs often write the same part as TO-247-3. Check the vendor drawing, because Vishay alone publishes more than one TO-247AC outline.
What is the TO-247 lead pitch?
5.46 mm BSC per Vishay outline documents 95223 and 96138, both of which state 0.215 in BSC. onsemi’s FPCN #16827 gives 5.45 mm BSC for the same feature; the difference is inch-to-millimetre rounding, not a real dimensional gap. That pitch is roughly double TO-220’s and is why TO-247 carries higher-voltage parts.
What is the fourth pin on a TO-247-4 for?
It is a source-sense or Kelvin connection: it ties to the same source metal but carries no load current, so the gate driver can reference a node that the switching di/dt does not move. Infineon’s AN 2013-05 shows this removes both the PCB lead inductance and the package bond-wire inductance from the gate loop.
Is TO-247 the same as TO-218?
No, though they are close enough to be confused. Per onsemi’s FPCN #16827, moving from TO-218 to TO-247 shrinks the mounting hole from 4.00–4.10 mm to 3.55–3.65 mm and shifts the hole position, while lead pitch stays effectively unchanged. TO-247 added the insulated hole and wider pin creepage.
Does a 4-pin TO-247 need a special gate driver?
Usually yes. Referencing the driver to source-sense makes its output stage float against power ground, and Infineon measured peaks of ±20 V or more there. Their recommendation is an isolated driver using coreless-transformer isolation, or a standard driver protected by an RC input filter.
What to do next
Before you order hardware: work from the vendor drawing tied to your part number, and size the screw and washer against ØP1, not ØP. The recess varies between drawings from the same supplier.
Before you choose 3-pin or 4-pin: find your switched current. Below roughly 15 A on a 45 mΩ-class device, Infineon’s own data says the source inductance is not your dominant loss.
If you go 4-pin: budget the driver first. An isolated gate driver and a 10 µF bias capacitor are part of the package decision, not an afterthought.
If you stay 3-pin: minimise the standoff. Two nanohenries at zero pin length against four at 5 mm is a layout choice with a measurable loss attached.
If you are replacing a TO-218 design: expect to change screw size and re-drill the sink. The lead pitch carries over; nothing else does.
