Surface mount packages fall into five working families: two-terminal chip passives, small-signal SOT/SC packages, tabbed power packages, leaded ICs, and leadless or ball-array ICs. Each family trades board area against pin count, thermal path, and how easily you can solder and inspect it. This guide gives real dimensions, JEDEC outline numbers, and selection rules for every common SMD package type — plus the reliability data most size charts leave out.
Key takeaways
- Package families rank by pin density: chip passives → SOT/SC → power tabs → gull-wing ICs (SOIC/QFP) → leadless/area-array (QFN/BGA).
- The imperial vs metric size-code collision is a real BOM hazard: “0603” means 1.6 × 0.8 mm in imperial but 0.6 × 0.3 mm in metric.
- Hand-solder cutoff sits around 0603 imperial; 0402 and below effectively require stencil, paste, and reflow.
- Leadless and area-array parts (QFN, BGA) need a soldered exposed pad or X-ray inspection — they are not drop-in replacements for leaded parts.
- Every plastic SMD carries a moisture sensitivity level (MSL) that dictates floor life before reflow; ignoring it cracks packages.
- Footprints follow IPC-7351B; package outlines are registered in JEDEC JEP95. Both trace to primary standards, not vendor blogs.
How SMD packages are named and standardized
A surface mount package is a component body designed to be soldered directly onto pads on the surface of a PCB, with no leads passing through the board. Terminations are either short gull-wing leads, J-leads, flat lands, or solder balls. Compared with through-hole parts, this cuts board area, shortens electrical paths, and suits automated pick-and-place assembly.
Two standards bodies govern the details. JEDEC registers the mechanical outline of each package in Publication 95 (JEP95) — the “MS-” and “MO-” drawing numbers you see in datasheets. IPC defines how you turn that outline into copper: IPC-7351B (June 2010, ~102 pages) specifies land-pattern geometry and a naming convention, and gives three density levels for every footprint — Level A (Most land, suffix M), Level B (Nominal, N), and Level C (Least, L). Level B is the default for general reflow production; Level A adds fillet for hand rework; Level C is for maximum density, and only if your assembler confirms the process window.
One naming trap causes more scrapped boards than any other. Chip-passive size codes exist in imperial (EIA) and metric (IEC) systems that look identical but mean different sizes. Imperial 0603 is 1.6 × 0.8 mm; metric 0603 is 0.6 × 0.3 mm. Always record which system your BOM and CAD library use, and prefer listing both codes.
[IMAGE 1: labeled cross-section of gull-wing, J-lead, no-lead (QFN), and BGA terminations on a PCB | alt: “Surface mount packages termination types: gull-wing, J-lead, QFN no-lead, and BGA solder ball on PCB”]
Chip passives: the size-code system
Resistors, capacitors, inductors, ferrite beads, and small LEDs share one size-code scheme. The four-digit code is the body’s length and width; in imperial it is hundredths of an inch, so 0402 is 0.04 in × 0.02 in, or 1.0 × 0.5 mm. Power handling scales with body volume, and so does the practical ability to place the part by hand.
| Imperial | Metric | Body (mm) | Typical resistor power¹ | Hand-solder |
| 01005 | 0402 | 0.4 × 0.2 | ~1/32 W (0.03 W) | No — reflow only |
| 0201 | 0603 | 0.6 × 0.3 | ~1/20 W (0.05 W)² | No — reflow only |
| 0402 | 1005 | 1.0 × 0.5 | ~1/16 W (0.063 W) | Difficult, with magnification |
| 0603 | 1608 | 1.6 × 0.8 | ~1/10 W (0.10 W) | Yes, with practice |
| 0805 | 2012 | 2.0 × 1.25 | ~1/8 W (0.125 W) | Yes — beginner-friendly |
| 1206 | 3216 | 3.2 × 1.6 | ~1/4 W (0.25 W) | Yes |
| 1210 | 3225 | 3.2 × 2.5 | ~1/3–1/2 W | Yes |
| 2010 | 5025 | 5.0 × 2.5 | ~3/4 W | Yes |
| 2512 | 6332 | 6.3 × 3.2 | ~1 W | Yes |
¹ Typical thick-film values; always use the datasheet’s derating curve above 70 °C. ² Confirmed against a Stackpole RMCF0201 listing on DigiKey (0.05 W, 0.6 × 0.3 mm).
Two rules matter here. First, do not downsize passives just to reclaim board area — a 0402 in a power path has little thermal mass and will drift or crack where an 0805 stays cool. Second, smaller chips tombstone more readily during reflow when pad heating is asymmetric, so balance the land pattern per IPC-7351.
Cost and availability reality check: small does not mean expensive. That 0201 resistor runs about $0.10 at quantity 1 but drops to roughly $0.004 each on a 10,000-piece reel (DigiKey, mid-2026). The size you can place reliably, not the unit price, is the real constraint.
Small-signal packages: SOT and SC families
Discrete transistors, MOSFETs, diodes, and small regulators live in the SOT (small-outline transistor) and SC families. The SOT-23 is the workhorse: JEDEC registers it as MO-178 (designator R-PDSO-G), with a 2.92 × 1.30 mm body and 0.95 mm lead pitch. Its 3-, 5-, and 6-lead variants share that body and pitch, and the 6-lead footprint accepts the 3- and 5-lead parts. The SOT-23-8 breaks the pattern, dropping to 0.65 mm pitch to fit eight leads on the same body.
Below SOT-23 sit smaller cousins for space-critical work: SOT-323 / SC-70 (2.0 × 1.25 mm body, 0.65 mm pitch) and SOT-523 (about a 1.8 × 1.8 mm footprint span, automated placement only). For a few hundred milliamps to a couple of watts, step up to SOT-89 or SOT-223, both of which add a metal heat-spreader tab. Naming is not consistent across vendors — SC-70 and SOT-323 describe nearly identical packages under different designations — so verify the land pattern against the specific datasheet.
Power packages: DPAK and D2PAK
When a MOSFET or regulator must shed real heat but stay surface-mounted, the tabbed power packages take over. DPAK (JEDEC TO-252; also SC-63, SOT-428) occupies roughly a 6.6 × 11.2 mm footprint span and is the surface-mount answer to the through-hole TO-220. D2PAK (TO-263, SOT404) is larger at about 10.4 × 17.0 mm and handles more power; a TO-263 THIN profile reduces height from the standard 4.5 mm to 2.0 mm.
Both packages dump heat through the drain tab into copper, so the PCB is the heatsink. Plan a copper pour of 1–2 cm² minimum for full rated current, plus a thermal-via array into inner layers on multilayer boards. Undersize that copper and the die runs hot regardless of the package rating.
[IMAGE 2: top-down footprint comparison from SOT-523 to D2PAK on a 1 mm grid | alt: “SMD transistor and power package footprint comparison from SOT-523 to DPAK and D2PAK”]
Leaded IC packages: SOIC to QFP
Gull-wing leaded ICs remain the easiest complex parts to assemble and inspect, because every joint is visible and probeable.
The SOIC (SO) package uses 1.27 mm pitch and covers 8–32 pins; JEDEC splits it into a narrow 3.9 mm body (MS-012, ~150 mil) and a wide 7.5 mm body (MS-013, ~300 mil). Watch a subtle interchange hazard: many vendors call the 5.3 mm EIAJ Type II body “SOP” while reserving “SOIC” for the JEDEC widths, so an “SOIC-16” from two suppliers is not guaranteed to share a footprint.
Shrinking the same idea gives SSOP, TSSOP (thin, ~1.0 mm profile, MO-153), and MSOP (micro, MO-187), typically at 0.65 mm pitch, plus TSOP for memory. For higher pin counts, the four-sided QFP family — TQFP (1.0 mm thick) and LQFP (1.4 mm) under MS-026 — reaches 256 pins at pitches commonly 0.4–0.8 mm. PLCC is the older J-leaded, socketable option at 1.27 mm pitch.
SOIC vs TSSOP is a common fork: choose SOIC for easy hand assembly and better power dissipation; choose TSSOP when height and area dominate and you have a reflow process.
Leadless and ball-array packages: QFN, DFN, LGA, BGA, WLCSP
Bottom-termination and area-array packages deliver the highest density, at the cost of hidden joints and stricter process control.
QFN (quad flat no-lead, JEDEC MO-220) and its two-sided sibling DFN (MO-229) put lands under the package edge plus a central exposed pad (EP) for heat and ground. The area saving is real: a 32-lead QFN in a 5 × 5 mm body is 25 mm², versus about 81 mm² for the equivalent 32-lead TQFP (7 × 7 mm body, 9 × 9 mm footprint) — roughly a 69% smaller land, per Infineon’s QFN design guide. QFN pitches run 0.5, 0.4, and 0.35 mm. LGA is the same idea with lands but no thermal pad; SON is the small-outline no-lead variant.
The QFN exposed pad is where designs fail quietly. Size the PCB thermal land 1:1 with the package EP, then add a thermal-via array: typically 0.25–0.33 mm drilled vias on 1.0–1.2 mm pitch, 9–25 vias depending on pad size, and via-fill is mandatory — open vias wick solder during reflow and create voids. onsemi’s thermal analysis shows that leaving vias unfilled collapses effective thermal conductivity to about 10.2 W/m·°C, gutting the heat path.
BGA (ball grid array) carries the highest pin counts on solder balls under the body: plastic PBGA and FBGA at 1.0/0.8 mm, µBGA/CSP at 0.5/0.4 mm, WLCSP (wafer-level chip-scale) down to 0.4/0.35/0.3 mm, and FCBGA for CPUs and FPGAs. Because the joints are hidden, BGAs demand X-ray inspection, tight reflow control, and often via-in-pad at fine pitch.
[IMAGE 3: underside views of QFN exposed pad, LGA lands, and BGA ball array | alt: “QFN exposed pad, LGA lands, and BGA solder ball array underside comparison”]
The SMD package selector
This is the table the ranking pages don’t build — every active family on one axis, with the attributes that actually drive a layout and sourcing decision.
| Family | Example | Pitch | Pin range | JEDEC outline | Thermal path | Hand-solder | Inspection |
| Small-signal | SOT-23 | 0.95 mm | 3–8 | MO-178 | Leads only | Yes | Visual |
| Small-signal | SC-70/SOT-323 | 0.65 mm | 3–6 | — | Leads only | Hard | Visual |
| Power tab | DPAK (TO-252) | Wide, tab | 3–5 | TO-252 | Drain tab + Cu | Yes | Visual |
| Power tab | D2PAK (TO-263) | Wide, tab | 3–7 | TO-263 | Drain tab + Cu | Yes | Visual |
| Gull-wing IC | SOIC | 1.27 mm | 8–32 | MS-012/013 | Leads | Yes | Visual |
| Gull-wing IC | TSSOP | 0.65 mm | 8–56 | MO-153 | Leads | Hard | Visual |
| Gull-wing IC | TQFP/LQFP | 0.4–0.8 mm | 32–256 | MS-026 | Leads | Hard | Visual |
| Leadless | QFN | 0.35–0.5 mm | 8–100+ | MO-220 | Exposed pad + vias | No | X-ray |
| Leadless | DFN | 0.5 mm | 6–10+ | MO-229 | Exposed pad | No | X-ray |
| Area array | PBGA/FBGA | 0.8–1.0 mm | 100s–1000s | per device | Balls + planes | No | X-ray |
| Area array | WLCSP | 0.3–0.4 mm | 4–100+ | per device | Balls | No | X-ray |
How to choose a surface mount package
Work the decision in this order:
- Pin count and pitch. Under ~20 pins, SOIC or QFN. Hundreds of pins, BGA is the only practical route.
- Thermal load. Dissipating more than ~0.5 W? Choose an exposed-pad or tabbed package (QFN-EP, DPAK, D2PAK) and design the copper and vias to match — the package alone does nothing without them.
- Assembly reality. Prototyping by hand or building low volume? Stay at SOIC/SOT-23/0603 and up. Fine-pitch QFN and BGA assume stencil, reflow, and X-ray.
- Board area and height. Tight z-height points to TSSOP, WLCSP, or a THIN power variant; tight xy-area points to QFN over TQFP.
- Lifecycle and second-sourcing. Confirm the exact JEDEC outline so an alternate supplier’s part drops into the same footprint, and check that the size is stocked as a reel, not just in cut-tape.
- Compliance. Verify RoHS/REACH, and for automotive require AEC-Q100 (ICs), AEC-Q101 (discretes), or AEC-Q200 (passives).
Reliability the size charts skip: MSL and reflow
Plastic SMD packages absorb ambient moisture. Heat them through reflow and trapped moisture flashes to steam, cracking the package — “popcorning.” IPC/JEDEC J-STD-020 classifies each package by moisture sensitivity level (MSL), a 1-to-6 scale that sets its floor life at 30 °C / 60% RH after the dry-pack bag is opened. J-STD-033 governs the dry-pack handling and bake-out that reset that clock.
| MSL | Floor life (30 °C / 60% RH) | Handling |
| 1 | Unlimited | No dry-pack needed |
| 2 | 1 year | Dry-pack + HIC |
| 2a | 4 weeks | Dry-pack + HIC |
| 3 | 168 hours | Dry-pack; track exposure |
| 4 | 72 hours | Dry-pack; tight tracking |
| 5 | 48 hours | Bake likely before reflow |
| 5a | 24 hours | Bake likely before reflow |
| 6 | Time on label | Mandatory bake before every reflow |
Reflow peak temperature is not one number. Lead-free SnAgCu solder has a liquidus near 217 °C, and J-STD-020 sets the classification peak (Tc) by package thickness and volume — thin, small packages qualify to 260 °C, while large BGAs are classified at 220 °C unless the supplier states otherwise. If a reel arrives from a broker with no exposure log, bake before use; that is far cheaper than reworking a board where several BGAs popcorned.
Five package mistakes that cause field returns
- Drawing the footprint from body size. The land pattern must add solder fillet and tolerance per IPC-7351; pads sized to the body alone bridge or starve.
- Forgetting the QFN exposed pad. No thermal land, no vias, or unfilled vias — the part overheats and voids. Size the land 1:1 and fill the vias.
- Mixing imperial and metric codes. A metric “0603” ordered as imperial arrives roughly four times too big. List both codes in the BOM.
- Downsizing passives into power paths. 0402 in a node dissipating real power drifts and cracks; use 0805 or larger for mechanical and thermal margin.
- Ignoring MSL on incoming reels. An MSL-3 BGA past floor life cracks during 260 °C reflow and fails months later. Track exposure and bake when in doubt.
FAQ
What are the different types of SMD packages?
They group into five families: chip passives (0201–2512), small-signal SOT/SC packages (SOT-23, SC-70), tabbed power packages (DPAK, D2PAK), leaded ICs (SOIC, TSSOP, QFP), and leadless or area-array ICs (QFN, DFN, LGA, BGA, WLCSP). Density and thermal capability rise across that list, while ease of hand assembly falls.
What is the smallest SMD package?
Among passives, 01005 (0.4 × 0.2 mm imperial) is the smallest in common use, with 008004 emerging. Among ICs, WLCSP parts reach 0.3 mm ball pitch and can be only slightly larger than the silicon die. Both require automated placement and reflow.
Which SMD package is easiest to hand-solder?
For passives, 0805 and 0603. For ICs, SOIC and SOT-23, because their gull-wing leads are visible and reachable with an iron. Leadless (QFN) and area-array (BGA) parts hide their joints and effectively need reflow.
What does QFN stand for, and why the exposed pad?
QFN is quad flat no-lead: lands sit under the package edge instead of on extended leads. The central exposed pad conducts heat and ground into the PCB, which is why it must be soldered down and backed by a thermal-via array to work.
What is the difference between imperial and metric SMD sizes?
The same four-digit code means different sizes in each system. Imperial 0603 is 1.6 × 0.8 mm; metric 0603 is 0.6 × 0.3 mm. Imperial (EIA) codes dominate ordering, but PCB dimensions are usually drawn in millimeters — always confirm which system a datasheet uses.
Is BGA a surface-mount package?
Yes. A ball grid array mounts on solder balls under the body and reflows onto surface pads, so it is fully surface-mount. Because the joints are hidden, BGAs need X-ray inspection and tighter reflow control than leaded parts.
What to do next
Pick the package the way you’ll build the board, not the way it looks in a catalog. Under 20 pins with light heat, default to SOIC or SOT-23 and keep passives at 0603 or larger — you can assemble and rework them by hand. Above roughly 0.5 W, commit to an exposed-pad or tabbed package and draw the copper and vias to match on the same day. Reach for QFN or BGA only once stencil, reflow, and X-ray are in your process, and lock the exact JEDEC outline so a second source drops in. Then check the MSL on every incoming reel before it hits the oven. Get those four decisions right and the package stops being a risk and becomes the cheapest reliability margin on the board.
Sources: JEDEC JEP95 Registered Outlines (jedec.org); IPC-7351B Land Pattern Standard (ipc.org); IPC/JEDEC J-STD-020 and TI SPRABY1 MSL/reflow application report (ti.com); Infineon AN72845 QFN design guidelines (infineon.com); onsemi AND8432 QFN thermal (onsemi.com); Analog Devices package thermal table (analog.com).
